Recent developments in the design of asynchronous circuits

Some recent developments in the design of asynchronous circuits are surveyed. The design process is considered in two parts. First, the communication behaviour of the component to be designed is formally specified and this specification is decomposed into a network of basic components. Second, the basic components are realized using gate circuits.\u3cbr/\u3e\u3cbr/\u3eIn the first part of the design process we use trace theory to reason about all possible sequences of events. Components are specified by regular-expression-like programs, called commands, whose semantics is based on directed trace structures. We formalize the concepts of speed-independent and delay-insensitive circuits in the context of a network of basic components.\u3cbr/\u3e\u3cbr/\u3eIn the second part we use switching theory for the analysis of gate circuits. Three different delay models are discussed: the feedback-delay, the gate-delay, and the gate-and-wire-delay model. The last two models correspond to speed-independent and delay-insensitive circuits, respectively. We point out that networks of components are commonly operated in the ‘input-output mode’ (where inputs may change as soon as outputs have responded to a previous input change), whereas gate circuits are usually operated in the ‘fundamental mode’ (where the entire gate circuit must stabilize before another input change is permitted).\u3cbr/\u3e\u3cbr/\u3eWe note that delay-insensitive gate circuits are unlikely to exist for most basic components. For this reason, it is important that analysis and design methods are developed using bounded-delay models