Logarithmic behavior of degradation dynamics in metal--oxide semiconductor devices

In this paper the authors describe a theoretical simple statistical modelling of relaxation process in metal-oxide semiconductor devices that governs its degradation. Basically, starting from an initial state where a given number of traps are occupied, the dynamics of the relaxation process is measured calculating the density of occupied traps and its fluctuations (second moment) as function of time. Our theoretical results show a universal logarithmic law for the density of occupied traps $\bar{} \sim \phi (T,E_{F}) (A+B \ln t)$, i.e., the degradation is logarithmic and its amplitude depends on the temperature and Fermi Level of device. Our approach reduces the work to the averages determined by simple binomial sums that are corroborated by our Monte Carlo simulations and by experimental results from literature, which bear in mind enlightening elucidations about the physics of degradation of semiconductor devices of our modern life

Understanding the Excess 1/f Noise in MOSFETs at Cryogenic Temperatures

Characterization, modeling, and development of cryo-temperature CMOS technologies (cryo-CMOS) have significantly progressed to help overcome the interconnection bottleneck between qubits and the readout interface in quantum computers. Nevertheless, available compact models still fail to predict the deviation of 1/f noise from the expected linear scaling with temperature ( $\textit{T}$ ), referred to as “excess 1/f noise”, observed at cryogenic temperatures. In addition, 1/f noise represents one of the main limiting factors for the decoherence time of qubits. In this article, we extensively characterize low-frequency noise on commercial 28-nm CMOS and on research-grade Ge-channel MOSFETs at temperatures ranging from 370 K down to 4 K. Our investigations exclude electron heating and bulk dielectric defects as possible causes of the excess 1/f noise at low temperatures. We show further evidence for a strong correlation between the excess 1/f noise and the saturation of the subthreshold swing (SS) observed at low temperatures. The most plausible cause of the excess noise is found in band tail states in the channel acting as additional capture/emission centers at cryogenic temperatures

Interaction Between Hot Carrier Aging and PBTI Degradation in nMOSFETs: Characterization, Modelling and Lifetime Prediction

Modelling of the interaction between Hot Carrier Aging (HCA) and Positive Bias Temperature Instability (PBTI) has been considered as one of the main challenges in nanoscale CMOS circuit design. Previous works were mainly based on separate HCA and PBTI instead of Interacted HCA-PBTI Degradation (IHPD). The key advance of this work is to develop a methodology that enables accurate modelling of IHPD through understanding the charging/discharging and generation kinetics of different types of defects during the interaction between HCA and PBTI. It is found that degradation during alternating HCA and PBTI stress cannot be modelled by independent HCI/PBTI. Different stress sequence, i.e. HCA-PBTI-HCA and PBTI-HCA-PBTI, lead to completely different degradation kinetics. Based on the Cyclic Anti-neutralization Model (CAM), for the first time, IHPD has been accurately modelled for both short and long channel devices. Complex degradation mechanisms and kinetics can be well explained by our model. Our results show that device lifetime can be underestimated by one decade without considering interaction

NBTI of Ge pMOSFETs: understanding defects and enabling lifetime prediction

Ge pMOSFETs are strong candidates for next technology nodes and record hole mobility has been reported for Al2O3/GeO2/Ge and HfO2/SiO2/Si-cap/Ge structures. Reliability, however, is still problematic and currently impedes the progress. Large NBTI exists in GeO2/Ge, and little is known about the defects. Si-cap/Ge device has superior reliability, but its lifetime, τ, cannot be predicted by power law extrapolation. This work demonstrates that the defects are different in Ge and Si devices. For the first time, a method is developed for Ge devices to restore the power law for NBTI kinetics, which enables τ prediction and process optimization

Characterization of DC performance and low-frequency noise of an array of nMOS Forksheets from 300 K to 4 K

The DC and low-frequency noise performance of an array of 800 parallel Forksheet MOSFETs were investigated by performing measurements over a wide temperature range from 300 K to 4 K. The array structure allowed to measure a representative average performance of the devices and provided a large effective area for 1/f noise analysis. Results showed an improvement in the saturation drain current when going from room temperature to cryogenic temperatures, with the subthreshold swing saturating around 100 K and the threshold voltage shifting by approximately 150 mV, following similar trends observed in Silicon cryogenic electronics. Additionally, the study confirms that the noise at cryogenic temperatures does not follow the commonly assumed linear scaling with temperature. This deviation from the linear scaling has been associated with the presence of tail states at the interface in bulk and silicon-on-insulator (SOI) devices. These results suggest that the excess 1/f noise in this advanced device architecture is not related to the device architecture but rather to the microscopic material properties of semiconductor/dielectric interfaces

Energy Distribution of Positive Charges in Al2O3/GeO2/Ge pMOSFETs

The high hole mobility of Ge makes it a strong candidate for end of roadmap pMOSFETs and low interface states have been achieved for the Al2O3-GeO2-Ge gate-stack. This structure, however, suffers from significant negative bias temperature instability (NBTI), dominated by positive charge (PC) in Al2O3/GeO2. An in-depth understanding of the PCs will assist in the minimization of NBTI and the defect energy distribution will provide valuable information. The energy distribution also provides the effective charge density at a given surface potential, a key parameter required for simulating the impact of NBTI on device and circuit performance. For the first time, this letter reports the energy distribution of the PC in Al2O3/GeO2 on Ge. It is found that the energy density of the PC has a clear peak near Ge Ec at the interface and a relatively low level between Ec and Ev. Below Ev at the interface, it increases rapidly and screens 20% of the Vg rise

NBTI-Generated Defects in Nanoscaled Devices: Fast Characterization Methodology and Modeling

Negative bias temperature instability (NBTI)-generated defects (GDs) have been widely observed and known to play an important role in device’s lifetime. However, its characterization and modeling in nanoscaled devices is a challenge due to their stochastic nature. The objective of this paper is to develop a fast and accurate technique for characterizing the statistical properties of NBTI aging, which can be completed in one day and thus reduce test time significantly. The fast speed comes from replacing the conventional constant voltage stress by the voltage step stress (VSS), while the accuracy comes from capturing the GDs without recovery. The key advances are twofold: first, we demonstrate that this VSS-GD technique is applicable for nanoscaled devices; second, we verify the 15 accuracy of the statistical model based on the parameters extracted from this technique against independently measured data. The proposed method provides an effective solution for GD evaluation, as required when qualifying a CMOS process