The dynamics of surface donor traps in AlGaN/GaN MISFETs using transient measurements and TCAD modelling

This paper presents a detailed and correlated (i) Id-Vg, (ii) Cgg-Vg, and (iii) transient analysis of donor traps in a SiN/GaN/AlGaN/GaN Metal-Insulator-Semiconductor Field-Effect Transistor (MISFET) fabricated on a silicon substrate. We explain for the first time that the long-time constants are due to the close coupling between the emission/capture processes on one hand and the transient transport of electrons across the GaN/AlGaN barrier on the other. Emission and capture time constants were extracted for several bias conditions and temperatures. Moreover, we have developed a TCAD model that consistently gives a good match to DC, AC, and transient experimental results

The effect of the surface fixed charge and donor traps on the C(V) and transfer characteristics of a GaN MISFET Experiment and TCAD simulations

Fixed charge and surface traps at the passivation/semiconductor interface play a major role in both the on-state and off-state performance as well as reliability of AlGaN/GaN high-voltage transistors. This paper reports a comprehensive analysis of these fixed charges and donor traps using C(V) measurements of a Metal-Insulator-Semiconductor Field-Effect Transistor (MISFET) fabricated alongside a highvoltage HEMT. For the first time, we have correlated the C(V) measurements with the Id-Vg characteristics of the MISFET and have carefully matched them with corresponding TCAD simulations for detailed explanations of the phenomena involved. We have also carried out capacitance measurements at different frequencies and investigated the formation of an inversion layer at the passivation/semiconductor interface and its dependence on the surface charge and donor traps as well as frequency

Modelling 2DEG charges in AlGaN/GaN heterostructures

In this paper we compare different approaches to calculating the charge density in the 2DEG layer of AlGaN/GaN HEMTs. The methods used are (i) analytical theory implemented in MATLAB, (ii) finite-element analysis using semiconductor TCAD software that implements only the Poisson and continuity equations, and (iii) 1D software that solves the Poisson and Schrödinger equations self-consistently. By using the 1D Poisson-Schrödinger solver, we highlight the consequences of neglecting the Schrödinger equation. We conclude that the TCAD simulator predicts with a reasonable level of accuracy the electron density in the 2DEG layer for both a conventional HEMT structure and one featuring an extra GaN cap layer. In addition, while the sheet charge density is not significantly affected by including Schrödinger, its confinement in the channel is found to be modified. © 2012 IEEE

Novel low-temperature processing of low noise SDDs with on-detector electronics

We have developed a fabrication process (SMART700° process) for monolithic integration of p-channel JFETs and silicon detectors. Processing steps of the SMART700° do not exceed 700°C. The integrated p-JFET has a minimum gate length of 1 μm. A relatively large width can be chosen to achieve a reasonable transconductance, while the JFET capacitance still matches the small capacitance of a detector. The feedback capacitor was also realized on-chip as a double-metal capacitor. In this paper we describe DC and noise characteristics of a silicon drift detector (SDD) with a p-JFET (W/L = 100/1) and a feedback capacitor integrated in the read-out anode (smart-SDD). The device has a transconductance of 1-3 mS, a top gate capacitance of ∼140 fF and a low leakage current (<10 nA/cm2 at room temperature). The smart-SDD with an active area of 3.8 mm2 has reached an energy resolution of ∼50 rms electrons at a temperature of 213 K. This relatively poor energy resolution is due to generation-recombination noise caused by defects produced by a deep n-implantation. Rapid thermal annealing (RTA) and excimer laser annealing (ELA) techniques are experimented to remove the implantation damage. The noise of p-JFETs annealed with RTA and ELA is also presented

Novel low-temperature processing of low noise SDDs with on-detector electronics

\u3cp\u3eWe have developed a fabrication process (SMART700° process) for monolithic integration of p-channel JFETs and silicon detectors. Processing steps of the SMART700° do not exceed 700°C. The integrated p-JFET has a minimum gate length of 1 μm. A relatively large width can be chosen to achieve a reasonable transconductance, while the JFET capacitance still matches the small capacitance of a detector. The feedback capacitor was also realized on-chip as a double-metal capacitor. In this paper we describe DC and noise characteristics of a silicon drift detector (SDD) with a p-JFET (W/L = 100/1) and a feedback capacitor integrated in the read-out anode (smart-SDD). The device has a transconductance of 1-3 mS, a top gate capacitance of ∼140 fF and a low leakage current (&lt;10 nA/cm\u3csup\u3e2\u3c/sup\u3e at room temperature). The smart-SDD with an active area of 3.8 mm\u3csup\u3e2\u3c/sup\u3e has reached an energy resolution of ∼50 rms electrons at a temperature of 213 K. This relatively poor energy resolution is due to generation-recombination noise caused by defects produced by a deep n-implantation. Rapid thermal annealing (RTA) and excimer laser annealing (ELA) techniques are experimented to remove the implantation damage. The noise of p-JFETs annealed with RTA and ELA is also presented.\u3c/p\u3

AIM - The method that caused the OEE to skyrocket

Electron mobility of AlGaN/GaN HEMTs is studied using a gate admittance-based technique. This analysis extends to electron densities as low as 4×10 10 cm -2 with good accuracy. Zero lateral electric field is applied, in contrast to conventional methods. At these low electron densities, the mobility can be a factor of ~50 less than that in the ON-state. We reveal a regime at low electron densities where the screening of the two dimensional electron gas (2-DEG) becomes negligible causing the mobility to be independent of electron concentration, suggesting percolative transport. This region defines the rate at which the channel depletes and is a strong indicator of the epitaxial control of the impurities in the GaN channel