34 research outputs found

    Low cost flip chip bonding on FR-4 boards

    No full text
    Flip-chip technology used directly on printed wiring boards offers minimisation of geometric parameters on conventional low-cost substrates as well as reduction in interconnect distances and inductances, particularly in high frequency applications. This paper describes the investigations of alternative low-cost flip-chip mounting processes using Au and Ni-Au bumps on organic laminate substrates (FR-4). The wiring planes of the PWBs are made by copper plating. The contact pads are topped with an electroplated Sn/Pb-63/37 eutectic solder. Flip-chip mounting was performed with and without flux application. The fatigue life of solder joints, which is limited by the thermal expansion mismatch between chip and substrate, could be significantly increased by a compatible flip-chip encapsulation process. First reliability results of metallurgical analysis and mechanical and electrical behaviour of the different flip-chip joints after thermal cycling between -55 degrees C and +125 degrees C are presented

    Chiptraeger-Anordnung sowie Chiptraeger zur Herstellung einer Chip-Gehaeusung

    No full text
    Chip carrier arrangement (23) comprising a chip carrier (23) for the production of a chip housing, said chip carrier having conductors (21) on a film carrier (20), said conductors being connected to contact surface metallizations (40) of the chip on the carrier foil front side facing a chip (39), and the free ends of which form a two-dimensionally distributed terminal area arrangement (42) for connection to an electronic component or a substrate, whereby the conductors (21) are arranged on the rear of the carrier foil (20), openings (28) are provided in the carrier foil (20) in the area of the contact area metallizations (40), the conductors are covered by a shadow mask to form the terminal area arrangement (42), and the thickness (s) of the carrier foil is smaller than or mainly equal to the height (h) of the contact area metallizations (40) on the chip surface

    Requirements for a Hybrid Dust-Gas-Standard: Influence of the Mixing Procedure on Safety Characteristics of Hybrid Mixtures

    No full text
    While developing a standard for the determination of safety characteristics for hybrid mixtures the authors discovered, that, beside the ignition source, the mixing procedure is the main difference between the single-phase standards for dusts and gases. The preparation of hybrid mixtures containing a flammable gas and a flammable dust in the 20 L-sphere can be realized in different ways. Either the flammable gas is filled only in the sphere or only in the dust container or in both. In previous works, almost always the first method is applied, without giving any information on the accuracy of the gas mixtures. In this work the accuracy of the gas mixtures and the results of the tests applying two methods of mixing were studied. No significant influence of the mixing method itself on the safety characteristics explosion pressure pex and the normalized rate of pressure rise (K-value) was found. Obviously, homogenization of the gas mixtures can be obtained sufficiently by the turbulence that is caused during the injection from the dust container into the explosion chamber within a short time. However, the mixing procedure has a great influence on the accuracy of the gas amount of the mixtures obtained. Without modifying the 20 L-sphere by installing precise pressure sensors, assuring its tightness and performing gas analysis, it must be expected, that the accuracy of the gas mixtures is very low. This has a significant influence on the measured safety characteristics and may lead to unsafe facilities or unnecessary expensive safety measures

    Green Tape Automation. Teilvorhaben: Untersuchung einer Flip-Chip-Technik auf Mehrlagen-Keramik-Substraten Abschlussbericht

    No full text
    The Flip Chip bonding technology offers numerous advantages compared with other, more conventional interconnection methods. In particular, the short interconnect distances allow fast signal response behaviour. Additional Flip-Chip bonding offers a very high interconnection density, the possibility to place connections over the whole active area of the flip chip bonded device and the possibility of self alignment. The FC mounting technology on green tape ceramic substrates offers economical and flexible solutions for a wide industrial application of multi chip modules including consumer products and industrial applications like automotive, telecommunication and medical electronic systems. The application of FC-technology on greentape multilayer substrates requires adapted metallization systems on substrate and chip. Fluxless soldering is possible directly on different thick film pattern metallizations. Concerning the process optimization and reliability investigations the Flip-Chip bonding experiments were performed using special test chips and test substrates. In order to study the thermomechanical behavior of the joints FEM-simulations were performed. In the project two bumping processes based on electroplated Au/Sn and Pb/Sn solders were developed. The bonding process was performed with the flip-chip bonder FC-950 from Carl Suess. For a fluxless soldering process, special aspects of reference were formulated. The fluxless flip chip bonding experiments were performed on different thick film metallization using substrates with an excellent flatness. The best mechanical and electrical results are achieved with Au/Sn solder bumps mounted on Pd/Ag metallizations. The influence of the contact height and the chip size on reliability were investigated by thermal cycling. The reliability of the joints could be significantly increased if an adequate underfill material was applied. This could be demonstrated by thermal cycling and ATC-testing of the fluxless mounted and encapsulated chips. In summary it could be shown that the application of a fluxless flip chip bonding technology with Au/Sn solder bumps on Pd/Ag thick film metallizations of Green Tape multilayer ceramic substrates is a promising interconnection method and opens new applications in the scope of advanced microsystems technologies. (orig.)SIGLEAvailable from TIB Hannover: F95B791 / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekBundesministerium fuer Forschung und Technologie (BMFT), Bonn (Germany)DEGerman

    Failure Analysis and Reliability Assessment in High Power Semiconductor Laser Packaging

    No full text
    corecore