Electrical correctness verification of MOS digital circuits using expert system and symbolic analysis techniques

SIGLEKULeuven Campusbibliotheek Exacte Wetenschappen / UCL - Université Catholique de LouvainBEBelgiu

Synthesis of Pipelined DSP Accelerators with Dynamic Scheduling

To construct complete systems on silicon, application specific DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology is presented to synthesize high throughput DSP functions into accelerator processors containing a datapath of highly pipelined, bit-parallel hardware units. Emphasis will be put on the definition of a controller architecture that allows efficient run-time schedules of these DSP algorithms on such highly pipelined data paths. The methodology will be illustrated by means of an image encoding filter bank. I. Introduction C OMPLEX digital systems such as the videophone terminal of figure 1 typically consist out of a heterogeneous mix of hardware blocks [1]: processor cores, general purpose macro blocks, and dedicated accelerator processors. These accelerator blocks are required to execute high performant DSP functions such as motion estimation and DCT/IDCT functions. In this paper we will concentrate on the ge..

Design of heterogeneous IC’s for mobile and personal communication systems

Mobile and personal communication systems form key market areas for the electronics industry of the nineties. Stringent requirements in terms of flexibility, performance and power dissipation, aredriving the development of integrated circuits into the direction of heterogeneous single-chip solutions. New IC architectures are emerging which contain the core of a powerful programmable processor, complemented with dedicated hardware, memory and interface structures. In this tutorial we will discuss the real-life design of a heterogeneous IC for an industrial telecom application: a reconfigurable mobile terminal for satellite communication. Based on this practical design experience, we will subsequently discuss a methodology for the design of heterogeneous ICs. Design steps that will be addressed include: system specification and refinement, data path and communication synthesis, and code generation for embedded processor cores

Design Space Exploration of All-Digital Symbol Timing Adjustment Architectures

In this contribution, a design space exploration of the various possible schemes for alldigital symbol timing adjustment of QAM signals is made. The exploration is guided by both performance degradation and implementation cost considerations. The BER performance degradation is obtained using a quasianalytic simulation approach, while the implementation cost is estimated by high level digital circuit synthesis. The results show that a good performance/implementation tradeoff is obtained by using baseband interpolation with an oversampling factor of three and adequate compensation. This timing adjustment circuit is now being applied in the design of a digital downstream CATV QAM receiver. 1 Introduction Currently, digital modems for broadband communication over coaxial or twisted pair access networks are of major interest. The high speed requirements together with a need for integration call for an all-digital solution, where all synchronization loops are implemented digitally on-chip...

Hardware reuse at the behavioral level

Standard interfaces for hardware reuse are currently de ned at the structural level. In contrast to this, our contribution de nes the reuse interface at the behavioral registertransfer (RT) level. This promotes direct reuse of functionality and avoids the integration problems of structural reuse. We present an object oriented reuse interface in C++ and show the use of it within two real-life designs.

Low Power Digital Frequency Conversion Architectures

. State-of-the-art data communication systems make extensive use of digital hardware. Besides baseband modulation functions, also the frequency tuning functions are now being shifted from analog to digital implementation. Integration, cost and ease of programming are the primary motivations for doing this. This paper presents an alternative to the traditional digital frequency conversion architectures. The proposed architecture achieves low power as well as high speed operation, and achieves this dual goal by reducing programmability. A multi-rate filtering approach is used, which is applicable for both upconversion and downconversion of quadrature modulated data. 1. Introduction In recent years, digital broadband communication on access networks have gained major interest [13]. Such networks are for instance telephone twisted pair [7] and hybrid fiber-coax CATV [3]. The modems inside these networks need to operate in a strongly regulated environment and should not interfere in presen..

A programming environment for the design of complex high speed ASICs

A C++ based programming environment for the design of complex high speed ASICs is presented. The design of a 75 Kgate DECT transceiver is used as a driver example. Compact descriptions, combined with e cient simulation and synthesis strategies are essential for the design of such a complex system. It is shown how a C++ programming approach outperforms traditional HDL-based methods.

CoWare -- A design environment for heterogeneous hardware/software systems

In this paper the design problems encountered when designing heterogeneous systems are studied and solutions to these problems are proposed. It will be shown why a single heterogeneous specification method ranging from concept to architecture is required and why it should cover issues as modularity, design for reuse, reuse of designs and reuse of design environments. A heterogeneous system design environment based on co-specification, co-simulation and cosynthesis is proposed and its application is illustrated by means of a spread spectrum based pager system

A Programming Environment for the Design of Complex High Speed ASICs

A C++ based programming environment for the design of complex high speed ASICs is presented. The design of a 75 Kgate DECT transceiver is used as a driver example. Compact descriptions, combined with efficient simulation and synthesis strategies are essential for the design of such a complex system. It is shown how a C++ programming approach outperforms traditional HDL-based methods. 1 Introduction In this contribution, we present a programming environment based on C++ that supports simulation, verification and synthesis of complex high speed ASICs for digital telecommunications. It is part of a larger environment that targets an automated synthesis path from the Matlab algorithm level to the VHDL architecture level [8]. In order to introduce the requirements put on to such an environment, a recent design experience will be documented. The design consists of a digital radiolink transceiver ASIC, residing in a DECT base station (figure 1). The chip processes DECT burst signals, receiv..

Synthesis of Multi-rate and Variable Rate Circuits for High Speed Telecommunications Applications

A design methodology for the synthesis of digital circuits used in high throughput digital modems is presented. The methodology spans digital modem design from the link level to the gate level. The methodology uses a C++-based untimed dataflow system description, which is gradually refined to an optimized, bit-true and clock cycle true C++-description. Through this refinement, a bridge from link level design semantics to architectural VHDL semantics is made within one and the same environment. 1 Introduction Currently there is a high interest in digital communication equipment for public access networks. Examples are modems for ADSL, VDSL, and up- and downstream HFC communication. Besides having high complexity and throughput requirements, these systems also need short development cycles. This calls for a design methodology that starts at high level and that provides for design automation as much as possible. Our contribution to existing design systems for telecommunications is a gr..