Design Space Exploration of All-Digital Symbol Timing Adjustment Architectures

Abstract

In this contribution, a design space exploration of the various possible schemes for alldigital symbol timing adjustment of QAM signals is made. The exploration is guided by both performance degradation and implementation cost considerations. The BER performance degradation is obtained using a quasianalytic simulation approach, while the implementation cost is estimated by high level digital circuit synthesis. The results show that a good performance/implementation tradeoff is obtained by using baseband interpolation with an oversampling factor of three and adequate compensation. This timing adjustment circuit is now being applied in the design of a digital downstream CATV QAM receiver. 1 Introduction Currently, digital modems for broadband communication over coaxial or twisted pair access networks are of major interest. The high speed requirements together with a need for integration call for an all-digital solution, where all synchronization loops are implemented digitally on-chip...