Double-channel hemt device and manufacturing method thereof

An HEMT device (1), comprising: a semiconductor body (15) including a heterojunction structure (13); a dielectric layer (7) on the semiconductor body; a gate electrode (8); a drain electrode (12), facing a first side (8') of the gate electrode (8); and a source electrode (10), facing a second side (8") opposite to the first side (8') of the gate electrode; an auxiliary channel layer (20), which extends over the heterojunction structure (13) between the gate electrode (8) and the drain electrode (12), in electrical contact with the drain electrode (12) and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode

Experimental and Numerical Evaluation of RON Degradation in GaN HEMTs during Pulse-Mode Operation

The on-resistance (RON) degradation in normally-OFF GaN high electron mobility transistors has been evaluated both experimentally and by means of numerical simulations by analyzing its drift during device pulse-mode operation. Experimental data showed that the device RON measured during the on-time interval of the switching period increased with time resulting in a thermally activated process with an activation energy $EA=0.83$ eV. For the first time, numerical simulations have been carried out in order to evaluate the device RON drift during pulse-mode operation and to understand the physical phenomena involved. A good qualitative agreement between experimental and simulated data has been obtained when considering in the simulated device simply a hole trap located at 0.83 eV from the GaN valence-band, an energy level which has been linked in previous works to carbon-doping within the GaN buffer

Hemt transistor including field plate regions and manufacturing process thereof

An HEMT transistor includes a semiconductor body having a semiconductive heterostructure. A gate region, of conductive material, is arranged above and in contact with the semiconductor body. A first insulating layer extends over the semiconductor body, laterally to the conductive gate region. A second insulating layer extends over the first insulating layer and the gate region. A first field plate region, of conductive material, extends between the first and the second insulating layers, laterally spaced from the conductive gate region along a first direction. A second field plate region, of conductive material, extends over the second insulating layer, and the second field plate region overlies and is vertically aligned with the first field plate region

Double-channel hemt device and manufacturing method thereof

An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode

Hemt transistor including field plate regions and manufacturing process thereof

HEMT transistor (50; 100; 150) having a semiconductor body (52) forming a semiconductive heterostructure (54, 56); a gate region (60), of conductive material, arranged above and in contact with the semiconductor body (52); a first insulating layer (58) extending above the semiconductor body, laterally to the conductive gate region (60); a second insulating layer (62) extending above the first insulating layer (58) and the gate region (60); a first field plate region (84), of conductive material, extending between the first and the second insulating layers (58), laterally spaced from the conductive gate region (60); and a second field plate region (85), of conductive material, extending above the second insulating layer (62), vertically aligned with the first field plate region (84)

Double-channel hemt device and manufacturing method thereof

An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode

Double-channel HEMT device and manufacturing method thereof

An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode

High electron mobility transistor and manufacturing method thereof

HEMT (1; 21; 31; 51) including a buffer layer (4), a hole-supply layer (6) on the buffer layer (4), a heterostructure (7) on the hole-supply layer (6), and a source electrode (16). The hole-supply layer (6) is made of P-type doped semiconductor material, the buffer layer (4) is doped with carbon, and the source electrode (16) is in direct electrical contact with the hole-supply layer (6), such that the hole-supply layer (6) can be biased to facilitate the transport of holes from the hole-supply layer (6) to the buffer layer (4)

HEMT transistor of the normally off type including a trench containing a gate region and forming at least one step, and corresponding manufacturing method

A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer

高电子迁移率晶体管

本公开涉及高电子迁移率晶体管。HEMT包括缓冲层、缓冲层上的空穴供应层、空穴供应层上的异质结构、以及源极电极。空穴供应层由P型掺杂半导体材料制成，缓冲层掺杂有碳，并且源极电极与空穴供应层直接电接触，使得空穴供应层可以被偏置以促进空穴从空穴供应层到缓冲层的传输。本公开的实施例使得能够在不降低击穿阈值以及在应力之前不增加通态电阻的值的情况下，消除应力对通态电阻的影响。This disclosure relates to high electron mobility transistor.HEMT includes buffer layer, the hole accommodating layer on buffer layer, heterojunction structure and source electrode on the accommodating layer of hole.Hole accommodating layer is made of p-type doped semiconductor materials, and undoped buffer layer has carbon, and source electrode is directly in electrical contact with hole accommodating layer, allows transmission of the hole accommodating layer by biasing to promote hole from hole accommodating layer to buffer layer.Embodiment of the disclosure makes it possible in the case where not reducing breakdown threshold and not increasing the value of on state resistance before stress, eliminates influence of the stress on state resistance