CMOS Circuits and Systems for Lab‐on‐a‐Chip Applications

Complementary metal oxide semiconductor (CMOS) technology allows the functional integration of sensors, signal conditioning, processing circuits and development of fully electronic integrated lab‐on‐a‐chip. On the other hand, lab‐on‐a‐chip is a technology which changed the traditional way by which biological samples are inspected and tested in laboratories. A lab‐on‐a‐chip consists of four main parts: sensing, actuation, readout circuit and microfluidic chamber. Lab‐on‐a‐chip gives the promise of many advantages including better and improved performance, reliability, portability and cost reduction. This chapter reviews the currently used lab‐on‐a‐chips based on CMOS technology. Also, this chapter presents and discusses the features of the existing CMOS based lab‐on‐a‐chips and their applications at the cell level

Adaptive multibit crosstalk-aware error control coding scheme for on-chip communication

The presence of different noise sources and continuous increase in crosstalk in the deep submicrometer technology raised concerns for on-chip communication reliability, leading to the incorporation of crosstalk avoidance techniques in error control coding schemes. This brief proposes joint crosstalk avoidance with adaptive error control scheme to reduce the power consumption by providing appropriate communication resiliency based on runtime noise level. By switching between shielding and duplication as the crosstalk avoidance technique and between hybrid automatic repeat request and forward error correction as the error control policies, three modes of error resiliencies are provided. The results show that, in reduced mode, the scheme achieves up to 25.3% power savings at 3-mm wire length as compared to the original nonadaptive scheme at the cost of only 3.4% power overhead in high protection mode

Multi-bit error control coding with limited correction for high-performance and energy- efficient network on chip

In the presence of deep submicron noise, providing reliable and energy-efficient network on-chip operation is becoming a challenging objective. In this study, the authors propose a hybrid automatic repeat request (HARQ)-based coding scheme that simultaneously reduces the crosstalk induced bus delay and provides multi-bit error protection while achieving high-energy savings. This is achieved by calculating two-dimensional parities and duplicating all the bits, which provide single error correction and six errors detection. The error correction reduces the performance degradation caused by retransmissions, which when combined with voltage swing reduction, due to its high error detection, high-energy savings are achieved. The results show that the proposed scheme reduces the energy consumption up to 51.7% as compared with other schemes while achieving the target link reliability level. Also, it shows improved network performance as compared with ARQ-based scheme and close to forward error correction-based schemes

Improved undetected error probability model for JTEC and JTEC-SQED coding schemes

The undetected error probability is an important measure to assess the communication reliability provided by any error coding scheme. Two error coding schemes namely, Joint crosstalk avoidance and Triple Error Correction (JTEC) and JTEC with Simultaneous Quadruple Error Detection (JTEC-SQED), provide both crosstalk reduction and multi-bit error correction/detection features. The available undetected error probability model yields an upper bound value which does not give accurate estimation on the reliability provided. This paper presents an improved mathematical model to estimate the undetected error probability of these two joint coding schemes. According to the decoding algorithm the errors are classified into patterns and their decoding result is checked for failures. The probabilities of the failing patterns are used to build the new models. The improved models have less than 1% error with respect to the simulation results and reflect in up to 60% higher mean time to failure as compared to available models

Crosstalk-aware multiple error detection scheme based on two-dimensional parities for energy efficient network on chip

Achieving reliable operation under the influence of deep-submicrometer noise sources including crosstalk noise at low voltage operation is a major challenge for network on chip links. In this paper, we propose a coding scheme that simultaneously addresses crosstalk effects on signal delay and detects up to seven random errors through wire duplication and simple parity checks calculated over the rows and columns of the two-dimensional data. This high error detection capability enables the reduction of operating voltage on the wire leading to energy saving. The results show that the proposed scheme reduces the energy consumption up to 53% as compared to other schemes at iso-reliability performance despite the increase in the overhead number of wires. In addition, it has small penalty on the network performance, represented by the average latency and comparable codec area overhead to other schemes

Optimizing FPGA-based hard networks-on-chip by minimizing and sharing resources

FPGA has become a favorable platform for Systems-on-Chip (SoC). As SoC gets larger, a Network-on-Chip (NoC) emerges as a promising solution for communication problems among SoC\u27s modules. Consequently, the importance of NoC on FPGAs has increased, not only to solve SoC\u27s communication problems but also as a solution to FPGA\u27s slow interconnects and to simplify Partial Dynamic Reconfiguration (PDR). Hard NoCs have better performance and consume less area and power than Soft NoCs. However, they are not configurable and they lead to a wasted area when the network is not in use. This makes the design of hard NoCs more critical to get an optimum performance while minimizing the wasted area as much as possible. In this paper, various NoC design parameters are evaluated to find the best-fit parameters that can be used in the non-configurable hard NoC design. In addition, different router architectures are investigated to select the optimum one for hard NoCs. Moreover, an efficient novel method for embedding the hard NoC inside the FPGA is proposed. The proposed NoC reduces the wasted area by using minimum and shareable resources. The NoC provides the FPGA with a high-performance communications infrastructure at a negligible cost. A total throughput of 0.33/1.3 Tbps (at a 32/128-bit flit width) is achieved on 65 nm technology at an added cost equivalent to the area of only 16/32 logic clusters

Simultaneous estimation of ledipasvir and sofosbuvir in bulk and its dosage forms by stability indicating RP-HPLC method

The fixed-dose ledipasvir-sofosbuvir combination offers an effective and well-tolerated pill for the treatment of chronic hepatitis C infection. Only a few analytical works were carried out to estimate the Ledipasvir and Sofosbuvir drug combination in the various dosage forms. This work aimed to simplify the estimation process using RP-HPLC methodology. The method was developed on a reversed phase Agilent C18 (4.6 x 150 mm, 5 µm) column. The isocratic elution process was performed using a mobile phase ratio of Methanol (70% v/v): Water (30 % v/v) with 0.6 ml/min flow rate. Elute was scanned using the PDA detector at the wavelength of 235 nm. The results of the elution process showed that the Ledipasvir and Sofosbuvir elute the peak at a concentration of 9 μg/ml and 40 μg/ml with retention times of 7.745 min and 2.345 min respectively. The percentage purity of Ledipasvir and Sofosbuvir was found to be 99.40 % w/v and 98.20 % w/v. The proposed method was found to be a high degree of precision and reproducibility. The percentage recovery was found to be 99.92 % for Ledipasvir and 99.82 % for Sofosbuvir. The LOD and LOQ were measured, and the results were within limits. The developed validation method can be applied for degradation evaluation of Ledipasvir and Sofosbuvir for the various dosage forms