Aggregate Factors In Bituminous Mixture Design.

PhDCivil engineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/187738/2/7311157.pd

Aggregate factors in bituminous mixture design

http://deepblue.lib.umich.edu/bitstream/2027.42/5696/5/bac5294.0001.001.pdfhttp://deepblue.lib.umich.edu/bitstream/2027.42/5696/4/bac5294.0001.001.tx

Randomized Single-Target Hot-Potato Routing

We present randomized hot-potato routing algorithms on d-dimensional meshes and on the n-dimensional hypercube. The algorithms are designed for routing many packets to a single destination, or a relatively small number of destinations. The important feature, which was not obtained previously, is that the algorithms utilize the higher in-degree of the nodes and are asymptotically optimal. A preliminary version was presented at the 3rd ISTCS 1995 (Israeli Symp. on the Theory of Computing Systems). y This work was supported in part by the French-Israeli grant for cooperation in Computer Science, and by a grant from the Israeli Ministry of Science. z Department of Computer Science, Technion, Haifa, Israel 32000. E-mail: [email protected] x Mathematics and Computer Science, Haifa University, Haifa, Israel 31905. E-mail: [email protected] -- Department of Computer Science, Technion, Haifa, Israel 32000. E-mail: [email protected] 1 Introduction In this work we..

Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications

Power analysis attacks are an effective tool to extract sensitive information using side-channel analysis, forming a serious threat to IoT systems-on-a-chip (SoCs). Embedded memories implemented with conventional 6T SRAM macrocells often dominate the area and power of these SoCs. In this paper, for the first time, we use silicon measurements to prove that conventional SRAM arrays leak valuable information and that their data can be extracted using power analysis attacks. In order to provide a power analysis resilient embedded memory and adhere to the area constraints of modern SoCs, we implement a low-cost impedance randomization unit, which is integrated into the periphery of a conventional 6T SRAM macro. Preliminary silicon measurements of a 55 nm test-chip implementing the proposed memory array demonstrate a significant information leakage reduction at a low-cost 1% area overhead and no speed and power penalties compared to a conventional SRAM design