Design Techniques for Power Efficient Millimeter Wave Transmitters in Nanoscale CMOS

The exponential growth of mobile device market has spurred considerable research interest. There are two killer applications of such market, namely wireless communication and positioning. Although the two application domains areseemingly different,there is a unifying property between the two applications. The bandwidth dictates the key performance metrics, namely peak data rate and precision for wireless comunication and positioning system, respectively. To facilitate high bandwidth, mm-wave operation is necessary. However, wideband operation at mm-wave comes with a power penalty. Therefore, this doctoral work focuses on developing smart circuit solution to ensure an optimal solution that balances bandwidth, linearity, and energy saving requirement. The first part of the dissertation addresses the energy efficiency issue of the GHz-wide multicarrier signal generation in an active tag (transmit unit) of a 60 GHz positioning system. Tackling the bandwidth problem is critical to achieve mm-precision. To come up with an optimum transmitter architecture, a holistic approach is employed in this work by means of hardware-algorithm co-design. The proposed architecture is thus geared to exploit the critical parameters for ranging, i.e. bandwidth and carrier frequency, and to eliminate the overhead circuit blocks caused by the ranging-irrelevant parameters. A proof of concept of the proposed 60 GHz transmitter is fabricated in a 40-nm GP CMOS technology, which incorporates a baseband subcarrier generator, a modulator, and a 60 GHz power amplifier. In this implementation, 16 subcarriers are generated with regular polarity inversion by means of an array of frequency division out of a 3 GHz input clock. The resulting BPSK-like waveform smartly fills the 6GHz band at the 60GHz band in a power optimized manner. Thanks to the low complexity yet effective waveform and generation method, power hungry building blocks, namely linear mixer, Digital-to-Analog Converter (DAC), and baseband filter are eliminated. From the measurement results, despite the harmonic rich spectrum due to the digital frequency divisions, a linear range computation is demonstrated. A standard deviation of 0.7-2.7 mm is achieved within the 5m measured distance with 5.4µs symbol duration. During the operation, the baseband subcarrier generator consumes an average power of 1.8mW out of 0.9V supply. The modulator and the power amplifier altogether consume 127mW. The total area of the transmitter is 1.1mm2. With such minimum area and power overhead, an optimal architecture is demonstrated to handle the compromise between the linearity and the average power consumption while meeting the mm-precision and ms-update rate target. The novelty in the second part of the dissertation lies within the transistor-level circuit design, whereby a mm-wave Doherty power amplifier is designed for 5G applications. In the upcoming 5G standard, a data rate in the range of tens of Gb/s is expected which motivates the shift towards mm-wave to gain more spectral real estate. On top of that, higher order modulation schemes and Orthogonal Frequency Division Multiplexing (OFDM) are expected to be employed to cram more bits in the band. These measures result in large Peak-to-Average Power Ratio (PAPR), forcing the PA to backoff up to 9 dB to maintain the linearity. With its prominent feature of efficiency enhancement at power backoff, the Doherty PA is considered the best candidate to address the problem. However, further research is needed to extend its bandwidth up to 2 GHz range and enable the amplification of multi-Gb/s data rate linearly. A 28-34 GHz transformer-based Doherty amplifier is fabricated in a 28-nm CMOS process as a proof-of-concept. This chip features wideband AM-PM compensation of the Doherty constituents, which addresses the wideband linearity issues of the Doherty topology. Furthermore, to achieve high power in the 28-nm CMOS technology, this work also features parallel-series-parallel power combining. Thanks to all of these techniques, the proposed Doherty amplifier supports the amplification of a 64-QAM signal with data rate of 15 Gb/s and achieves PSAT of 19.8 dBm. These numbers are the state-of-art performance in the 28nm bulk CMOS technology. In conclusion, the two proof-of-concepts of the two key application domains namely wireless communication and positioning system have demonstrated that high bandwidth, and thus mm-wave operation, are critical to achieve the respective key performance metrics. Based on this conclusion, we propose two solutions in the architecture level and the circuit level, respectively, to minimize the energy consumption such that the target precision and data rate are reached despite the mm-wave operation.nrpages: 226status: publishe

A 32 GHz20 dBm-PSAT Transformer-based Doherty Power Amplifier for multi-Gb/s 5G Applications in 28 nm Bulk CMOS

© 2017 IEEE. This paper presents a 32 GHz transformer-based Doherty power amplifier (PA) in a 28 nm bulk CMOS process. There are two techniques proposed: linearization by means of AM-PM and AM-AM compensation of the class AB and the class C amplifiers; and parallel-series-parallel power power combiner, wherein a current-mode parallel combiner complements the Doherty's voltage-mode series combiner to boost the output power. A saturated output power (PSAT ) of 19.8 dBm and an OP1dB of 16 dBm are accomplished from 1V supply while supporting 15 Gb/s 64-QAM amplification at 11.7 dBm average output power. The chip achieves 21% PAE at PSAT and occupies 0.59 mm2 active area.status: publishe

Doherty techniques for 5G RF and mm-wave Power Amplifiers

© 2016 IEEE. 5G poses severe challenges to PA design. In the first place, output power and efficiency are of prime importance because of battery lifetime. The tradeoff between linear output power and efficiency is typically challenged by the high PAPR due to QAM modulation and/or OFDM techniques. But this important trade-off is challenged even more in 5G due to the high bandwidth requirements. Furthermore, the shift to higher frequencies, where more unused spectrum is available, also puts a burden on the overall PA architecture.status: publishe

A mm-Precise 60 GHz Transmitter in 40 nm CMOS for Discrete-Carrier Indoor Localization

This paper presents a multicarrier 60 GHz transmitter for distance measurement (ranging) in an indoor wireless localization system, achieving mm-precision with high update rate. The architecture comprises a baseband subcarrier generator, an upconverter, and a power amplifier. There are three key innovations, all stemming from careful hardware-algorithm co-design: 1) efficient frequency planning of the 6 GHz-wide band; 2) power-efficient multicarrier signal generation by means of digital frequency divisions exploiting the phase-based time-of-arrival ranging algorithm; and 3) PAPR reduction to enable efficient operation of the power amplifier. By implementing these key techniques, 0.7-2.7 mm precision is achieved over 5 m measured distance with 5.4 μs symbol duration. During operation, the core digital subcarrier generator generates 16 non-equidistant subcarriers from a 3 GHz input clock, while consuming an average power of 1.8 mW out of 0.9V supply. The upconverter and the power amplifier altogether consume around 127 mW. The total area of the transmitter is 1.1 mm2. The chip is fabricated in a 40nm general purpose CMOS process.status: publishe

A 60GHz transmitter in 40nm CMOS achieving mm-precision for discrete-carrier localization

This paper presents an efficient multicarrier 60GHz transmitter for distance measurement (ranging) in an indoor wireless localization system. By exploiting hardware-algorithm co-design, a high precision, high update rate, yet power efficient transmitter architecture is achieved, which comprises subcarrier generation through frequency division, an upconverter, and a power amplifier. An efficient frequency generation through digital design is ensured by means of co-design with the amplitude nonlinearity-tolerant algorithm. In consequence, conventional power hungry baseband blocks, such as DAC and OFDM processor, are avoided. Moreover, symbol selection is performed to minimize PAPR. The transmitter achieves 0.7-2.4mm precision demonstrated over a distance of 4m. During operation, the core digital subcarrier generator generates 16 non-equidistant subcarriers, while consuming an average power of 1.8mW out of 0.9V supply with an input clock of 3GHz. The upconverter and the power amplifier altogether consume around 127mW. The total active area of the core transmitter circuit is 0.9mm2. The chip is fabricated in a 40nm general purpose CMOS process.status: publishe

An OFDM based local positioning system

A sub cm precision local positioning system with a high update rate is proposed. This precision is possible because the high bandwidth that is available on 60 GHz. Using a OFDM based modulation scheme a very efficient ToA estimator can be made. Commercial CMOS technologies smaller than 40nm enable the use of mm-wave in a cost efficient manner. Two prototype ASICs have been made to implement the receiver which also includes a high speed analog to digital converter. The second ASIC implements the transmitter, it contains the modulator and power amplifier. To enable processing at the required update rates the algorithms for ToA estimation and localization are implemented on an FPGA.status: publishe