Design Techniques for Power Efficient Millimeter Wave Transmitters in Nanoscale CMOS

Abstract

The exponential growth of mobile device market has spurred considerable research interest. There are two killer applications of such market, namely wireless communication and positioning. Although the two application domains areseemingly different,there is a unifying property between the two applications. The bandwidth dictates the key performance metrics, namely peak data rate and precision for wireless comunication and positioning system, respectively. To facilitate high bandwidth, mm-wave operation is necessary. However, wideband operation at mm-wave comes with a power penalty. Therefore, this doctoral work focuses on developing smart circuit solution to ensure an optimal solution that balances bandwidth, linearity, and energy saving requirement. The first part of the dissertation addresses the energy efficiency issue of the GHz-wide multicarrier signal generation in an active tag (transmit unit) of a 60 GHz positioning system. Tackling the bandwidth problem is critical to achieve mm-precision. To come up with an optimum transmitter architecture, a holistic approach is employed in this work by means of hardware-algorithm co-design. The proposed architecture is thus geared to exploit the critical parameters for ranging, i.e. bandwidth and carrier frequency, and to eliminate the overhead circuit blocks caused by the ranging-irrelevant parameters. A proof of concept of the proposed 60 GHz transmitter is fabricated in a 40-nm GP CMOS technology, which incorporates a baseband subcarrier generator, a modulator, and a 60 GHz power amplifier. In this implementation, 16 subcarriers are generated with regular polarity inversion by means of an array of frequency division out of a 3 GHz input clock. The resulting BPSK-like waveform smartly fills the 6GHz band at the 60GHz band in a power optimized manner. Thanks to the low complexity yet effective waveform and generation method, power hungry building blocks, namely linear mixer, Digital-to-Analog Converter (DAC), and baseband filter are eliminated. From the measurement results, despite the harmonic rich spectrum due to the digital frequency divisions, a linear range computation is demonstrated. A standard deviation of 0.7-2.7 mm is achieved within the 5m measured distance with 5.4µs symbol duration. During the operation, the baseband subcarrier generator consumes an average power of 1.8mW out of 0.9V supply. The modulator and the power amplifier altogether consume 127mW. The total area of the transmitter is 1.1mm2. With such minimum area and power overhead, an optimal architecture is demonstrated to handle the compromise between the linearity and the average power consumption while meeting the mm-precision and ms-update rate target. The novelty in the second part of the dissertation lies within the transistor-level circuit design, whereby a mm-wave Doherty power amplifier is designed for 5G applications. In the upcoming 5G standard, a data rate in the range of tens of Gb/s is expected which motivates the shift towards mm-wave to gain more spectral real estate. On top of that, higher order modulation schemes and Orthogonal Frequency Division Multiplexing (OFDM) are expected to be employed to cram more bits in the band. These measures result in large Peak-to-Average Power Ratio (PAPR), forcing the PA to backoff up to 9 dB to maintain the linearity. With its prominent feature of efficiency enhancement at power backoff, the Doherty PA is considered the best candidate to address the problem. However, further research is needed to extend its bandwidth up to 2 GHz range and enable the amplification of multi-Gb/s data rate linearly. A 28-34 GHz transformer-based Doherty amplifier is fabricated in a 28-nm CMOS process as a proof-of-concept. This chip features wideband AM-PM compensation of the Doherty constituents, which addresses the wideband linearity issues of the Doherty topology. Furthermore, to achieve high power in the 28-nm CMOS technology, this work also features parallel-series-parallel power combining. Thanks to all of these techniques, the proposed Doherty amplifier supports the amplification of a 64-QAM signal with data rate of 15 Gb/s and achieves PSAT of 19.8 dBm. These numbers are the state-of-art performance in the 28nm bulk CMOS technology. In conclusion, the two proof-of-concepts of the two key application domains namely wireless communication and positioning system have demonstrated that high bandwidth, and thus mm-wave operation, are critical to achieve the respective key performance metrics. Based on this conclusion, we propose two solutions in the architecture level and the circuit level, respectively, to minimize the energy consumption such that the target precision and data rate are reached despite the mm-wave operation.nrpages: 226status: publishe