5 research outputs found
New Voter Design Enabling Hot Redundancy for Asynchronous Network Nodes
The use of the Karhunen-Loéve Transform (KLT) for spectral decorrelation in compression of hyperspectral satellite images results in improved performance. However, the KLT algorithm consists of sequential processes, which are computationally intensive, such as the covariance matrix computation, eigenvector evaluation and matrix multiplications. These processes slow down the overall computation of the KLT transform significantly. The traditional KLT can only offer lossy compression; therefore, a reversible KLT algorithm, named the Integer KLT, is used for lossless compression. The Integer KLT includes more computational processes and, hence, it requires a longer processing time. The acceleration of these processes within the context of limited power and hardware budgets is the main objective of this paper. The computations of each of these processes are investigated thoroughly. Subsequently, a novel adaptive architecture for the computation of the KLT and the Integer KLT is proposed. The proposed system improves the traditional KLT performance compared with a previous architecture, and offers significant improvement for hyperspectral data with a larger spectral dimension. The experiments showed an overall improvement of up to 4.9%, 11.8% and 18.4% for 8, 16 and 32 spectral bands, respectively. In addition, this paper addresses novel hardware aspects of the Integer KLT implementation. The scalability of this hardware architecture can offer much higher level of parallel computing than processor platforms
Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture
Sterpone L, Sabena D, Ullah A, Porrmann M, Hagemeyer J, Ilstad J. Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture. In: Adaptive Hardware and Systems (AHS), 2013 NASA/ESA Conference on. IEEE; 2013: 184-188.The usage of reconfigurable systems is of increasingly interest for space and avionic applications. In the present work we propose an implementation flow for hardening Dynamically Reconfigurable Processing Module (DRPM) Systems implemented on modern SRAM-based FPGAs. We also report neutron radiation testing campaigns when the system is implemented on Xilinx Virtex-4 and Virtex-5 SRAM-based FPGAs. Experimental results performed by heavy-ions radiation experiments and fault injection campaigns demonstrate the effectiveness of the proposed method
AXI-based SpaceFibre IP CORE Implementation
Cozzi D, Jungewelter D, Kleibrink D, et al. AXI-based SpaceFibre IP CORE Implementation. Presented at the 6th International SpaceWire Conference, Athens, Greece
Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications
Köster M, Hagemeyer J, Margaglia F, et al. Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications. In: DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing. 2011
Implementation of a Dynamically Reconfigurable Processing Module for SpaceWire Networks.
Dittmann F, Linke M, Hagemeyer J, et al. Implementation of a Dynamically Reconfigurable Processing Module for SpaceWire Networks. In: Proceedings of the International SpaceWire Conference 2010. 2010: 193-196.The ESA-project "FPGA based generic module and dynamic reconfigurator" targets
the development of a hardware architecture, called DRPM (for Dynamically
Reconfigurable Processing Module). The goal of the DRPM is to develop a system
that allows for the adaptation of hardware components in flight at run-time. This is
enabled by the implementation of an SRAM-FPGA-based partially reconfigurable
core, which is embedded into a system hosting a reconfiguration controller and a
system controller providing suitable interfaces for space applications. Maximum
flexibility is realized by implementing SpaceWire interfaces that enable the DRPM
integration into a SpaceWire network. Moreover, the SpaceWire RMAP protocol is
used for remote access to registers and memory banks of the DRPM