Edge Termination and RESURF Technology in Power Silicon Carbide Devices

The effect of the electrical field enhancement at the junction discontinuities and its impact on the on-state resistance of power semiconductor devices was investigated. A systematic analysis of the mechanisms behind the techniques that can be used for the edge termination in power semiconductor devices was performed. The influence of the passivation layer properties, such as effective interface charge and dielectric permittivity, on the devices with different edge terminations was analyzed using numerical simulation. A compact analytical expression for the optimal JTE dose was proposed for the first time. This expression has been numerically evaluated for different targeted values of the blocking voltage and the maximum electric field, always resulting in the optimal field distribution that does not require further optimization with 2-D device simulator. A compact set of rules for the optimal design of super-junction power devices was developed. Compact analytical expressions for the optimal dopings and dimensions of the devices employed the field compensation technique are derived and validated with the results of numerical simulations on practical device structures. A comparative experimental study of several approaches used for the edge termination in SiC power diodes and transistors was performed. The investigated techniques included the mesa termination, high-k termination, JTE, and the combination of JTE and field plate edge termination. The mesa edge termination was found to be the most promising among the techniques investigated in this work. This stand-along technique satisfied all the imposed requirements for the ?ideal? edge termination: performance, reproducibility (scalability), and cost-efficiency. First of all, it resulted in the maximum one-dimensional electric field (E1DMAX) at the main device junction equal to 2.4 MV/cm or 93% of the theoretical value of critical electric field in 4H-SiC. Secondly, the measured E1DMAX was found to be independent of the voltage blocking layer parameters that demonstrate the scalability of this technique. Lastly, the implementation of this technique does not require expensive fabrication steps, and along with an efficient use of the die area results in the low cost and high yield

{CdTe}-based thin film photovoltaics: Recent advances, current challenges and future prospects

Cadmium telluride (CdTe)-based cells have emerged as the leading commercialized thin film photovoltaic technology and has intrinsically better temperature co-efficients, energy yield, and degradation rates than Si technologies. More than 30 GW peak (GWp) of CdTe-based modules are installed worldwide, multiple com-panies are in production, modules are shipping at up to 18.6% efficiency, and lab cell efficiency is above 22%. We review developments in the science and technology that have occurred over approximately the past decade. These achievements were enabled by manufacturing innovations and scaling module production, as well as maximizing photocurrent through window layer optimization and alloyed CdSexTe1-x (CST) absorbers. Improved chlorine passivation processes, film microstructure, and serendipitous Se defect passivation significantly increased minority carrier lifetime. Efficiencies >22% have been realized for both Cu and As doped CST-based cells. The path to further efficiency gains hinges primarily on increasing open circuit voltage (Voc) and fill factor (FF) through innovations in materials, fabrication methods, and device stacks. Replacing the longstanding Cu doping with As doping is resulting in better module stability and is being translated to large-scale production. To realize 25% efficiency and >1 V Voc, research and development is needed to increase the minority carrier lifetime beyond 100 ns, reduce grain boundary and interface recombination, and tailor band diagrams at the front and back interfaces. Many of these goals have been realized separately however combining them together using scalable manufacturing approaches has been elusive to date. We review these achievements and outstanding opportunities for this remarkable photovoltaic technology

CdTe-based thin film photovoltaics: recent advances, current challenges and future prospects

Cadmium telluride (CdTe)-based cells have emerged as the leading commercialized thin film photovoltaic technology and has intrinsically better temperature coefficients, energy yield, and degradation rates than Si technologies. More than 30 GW peak (GWp) of CdTe-based modules are installed worldwide, multiple companies are in production, modules are shipping at up to 18.6% efficiency, and lab cell efficiency is above 22%. We review developments in the science and technology that have occurred over approximately the past decade. These achievements were enabled by manufacturing innovations and scaling module production, as well as maximizing photocurrent through window layer optimization and alloyed CdSexTe1-x (CST) absorbers. Improved chlorine passivation processes, film microstructure, and serendipitous Se defect passivation significantly increased minority carrier lifetime. Efficiencies >22% have been realized for both Cu and As doped CST-based cells. The path to further efficiency gains hinges primarily on increasing open circuit voltage (Voc) and fill factor (FF) through innovations in materials, fabrication methods, and device stacks. Replacing the longstanding Cu doping with As doping is resulting in better module stability and is being translated to large-scale production. To realize 25% efficiency and >1 V Voc, research and development is needed to increase the minority carrier lifetime beyond 100 ns, reduce grain boundary and interface recombination, and tailor band diagrams at the front and back interfaces. Many of these goals have been realized separately however combining them together using scalable manufacturing approaches has been elusive to date. We review these achievements and outstanding opportunities for this remarkable photovoltaic technology.</p