A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers

Low off-state Leakage Currents in AlGaN/GaN High Electron Mobility Transistors By Employing A Highly Stressed SiNx Surface Passivation Layer

In this study, the impact of the stress in SiNx surface passivation layers on off-state drain and gate leakage currents and off-state breakdown voltage in AlGaN/GaN High Electron Mobility Transistors (HEMTs) is assessed. The SiNx films were deposited at room temperature by inductively coupled plasma chemical vapour deposition (ICP-CVD). Compared to unpassivated devices, the off-state drain and gate leakage currents of AlGaN/GaN HEMTs is increased by up to 2 orders of magnitude for a 200 nm thick SiNx passivation layer with 309 MPa compressive stress. The use of a bilayer SiNx passivation scheme comprising 70 nm SiNx with 309 MPa compressive stress followed by 130 nm SiNx with 880 MPa compressive stress resulted in off-state drain and gate leakage currents reduced by up to 1 order of magnitude when compared to unpassivated devices

Low off-state Leakage Currents in AlGaN/GaN High Electron Mobility Transistors By Employing A Highly Stressed SiNx Surface Passivation Layer

In this study, the impact of the stress in SiNx surface passivation layers on off-state drain and gate leakage currents and off-state breakdown voltage in AlGaN/GaN High Electron Mobility Transistors (HEMTs) is assessed. The SiNx films were deposited at room temperature by inductively coupled plasma chemical vapour deposition (ICP-CVD). Compared to unpassivated devices, the off-state drain and gate leakage currents of AlGaN/GaN HEMTs is increased by up to 2 orders of magnitude for a 200 nm thick SiNx passivation layer with 309 MPa compressive stress. The use of a bilayer SiNx passivation scheme comprising 70 nm SiNx with 309 MPa compressive stress followed by 130 nm SiNx with 880 MPa compressive stress resulted in off-state drain and gate leakage currents reduced by up to 1 order of magnitude when compared to unpassivated devices

(Invited) towards a vertical and damage free post-etch InGaAs fin profile: dry etch processing, sidewall damage assessment and mitigation options

Based on current projections, III-Vs are expected to replace Si as the n-channel solution in FinFETs at the 7nm technology node. The realisation of III-V FinFETs entails top-down fabrication via dry etch techniques. Vertical fins in conjunction with high quality sidewall MOS interfaces are required for high-performance logic devices. This, however, is difficult to achieve with dry etching. Highly anisotropic etching required of vertical fins is concomitant with increased damage to the sidewalls, resulting in the quality of the sidewall MOS interface being compromised. In this work, we address this challenge in two stages by first undertaking a systematic investigation of dry etch processing for fin formation, with the aim of obtaining high resolution fins with vertical sidewalls and clean etch surfaces. In the second stage, dry etch process optimisation and post-etch sidewall passivation schemes are explored to mitigate the damage arising from anisotropic etching required for the realisation of vertical fins

Demonstration of III-V fins with vertical sidewalls using Cl₂/CH₄/H₂/O₂ dry etch chemistry in conjunction with digital etching for recovery of etch damage

No abstract available

10 nm vertical In_0.53Ga_0.47As line etching process for III-V MOSFET fabrication by using inductively coupled plasma (ICP) etcher in C_l2/CH₄/H₂ chemistry

No abstract available

Development of III-V MOSFET process modules compatible with silicon ULSI manufacture

To address issues associated with continual scaling of the International Technology Roadmap for Semiconductors (ITRS) [1] to follow Moore's Law, MOSFETs with high mobility channel materials are now being seriously considered. As a result, there has been a significant expansion in research into III-V MOSFETs as a potential n-channel device solution. For ultimate CMOS exploitation, self-aligned III-V MOSFETs with sub-20 nm critical dimensions will have to be realized using silicon compatible process flows. This paper reviews the current status of III-V MOSFET research from the perspective of silicon ULSI process compatibility

First Demonstration of Cluster Tool Based ICP Etching of (100) and (110) InGaAs MOSCAPs Followed by In-Situ ALD Deposition of HfO2 Including Nitrogen and Hydrogen Plasma Passivation for Non-Planar III-V MOSFETs

No abstract available

Energy-band parameter of atomic layer deposited Al2O3 & sulphur passivated molecular beam epitaxially grown (110) In0.53Ga0.47As surfaces

Based on sulphur passivation (10% (NH<sub>4</sub>)<sub>2</sub>S, 20min), the interface of MOS capacitors between atomic-layer-deposited Al<sub>2</sub>O<sub>3</sub> and (110)-oriented p-type In<sub>0.53</sub>Ga<sub>0.47</sub>As layers indicate the capability of Fermi level movement and minority carrier inversion. C<sub>ox</sub> has effectively extracted by Gm/<i>w</i> and -<i>w</i>dC/d<i>w</i>. Forming gas annealing (N<sub>2</sub>:H<sub>2</sub> 5%:95% at 350<sup>o</sup>C, 30min) improves minority carrier response and the interface trap density around the midgap estimated to be 4.4x10<sup>12</sup> (1.6x10<sup>12</sup>) cm<sup>-2</sup>eV<sup>-1</sup> before (and after) FGA. Moreover, Fowler-Nordheim (FN) tunneling current provides the conduction band offset at the surface between Al<sub>2</sub>O<sub>3</sub> and In<sub>0.53</sub>Ga<sub>0.47</sub>As (110)-oriented layer is ~1.81eV and the barrier height is estimated to be the same after FGA. Finally, the band parameter of Al<sub>2</sub>O<sub>3</sub> and In<sub>0.53</sub>Ga<sub>0.47</sub>As (110)-oriented layer has been firstly reported