Integration of ultrathin silicon chips

In this work the mechanical behavior of ultrahin silicon chips during gold/tin bump reflow and during flip chip soldering onto polyimide tapes was analyzed. The experiments and analyses are a contribution to the research area of flex systems based on solder connections between extremely thin chips and flexible substrates. Silicon test chips with thicknesses between 3.5 and 45 µm were fabricated using the Dicing-by-Thinning process (DbyT process). At the start of this process trenches are dry-etched into the front side of the silicon wafer along the designated chip edges using a resist for masking. Then, the back side of the wafer is thinned (using a sequence of lapping, chemical-mechanical polishing, and wet etching steps) until the front side trenches are reached, resulting in the separation of the chips. Prior to the DbyT process the silicon wafers were plated with gold tracks and solder bumps, consisting of a gold base, a nickel diffusion barrier, and a gold-tin solder stack. Complementary structures were similarly fabricated on polyimide tapes with a thickness of 5 µm, that later served as substrates for the silicon chips. At the center of the investigation are the observed silicon deformations and their simulation based on the finite element method (FEM) and using a downsized model. Global and local deformations (that is deformations on the chip-level and bump-level, respectively) are analyzed and adapted FEM models are developed based on the simulation tool ANSYS 11.0. Because the observed deformations are a result of the process history as a whole, the mechanical stress in the electroplated layers, as well as deformations during heating and cooling of the reflow and soldering processes, were taken into account in the conception of the model. Using long lines of solder deposit in several test chips, the orientation of the deformation could be directly influenced and their magnitude could be increased, allowing the deformations to be observed and measured during the soldering process as a function of temperature and time. These data and their dependence on the silicon thickness and the solder bump geometry were used to significantly improve the model, which initially was based mostly on material data from the literature. With the improvement of the model a good agreement between simulated and measured deformations was mostly achieved. It was also shown, that the anisotropic mechanical properties of silicon dominate the orientation of the bending axis in "thick" chips, while in very thin chips the metallic structures have an increasing influence. It was also shown, that, assuming an adapted design and silicon and metal structure thicknesses, reflowed silicon chips could be fabricated without any resulting global deformation. This can significantly improve chip handling during subsequent processes

Integration of ultrathin silicon chips

In this work the mechanical behavior of ultrahin silicon chips during gold/tin bump reflow and during flip chip soldering onto polyimide tapes was analyzed. The experiments and analyses are a contribution to the research area of flex systems based on solder connections between extremely thin chips and flexible substrates. Silicon test chips with thicknesses between 3.5 and 45 µm were fabricated using the Dicing-by-Thinning process (DbyT process). At the start of this process trenches are dry-etched into the front side of the silicon wafer along the designated chip edges using a resist for masking. Then, the back side of the wafer is thinned (using a sequence of lapping, chemical-mechanical polishing, and wet etching steps) until the front side trenches are reached, resulting in the separation of the chips. Prior to the DbyT process the silicon wafers were plated with gold tracks and solder bumps, consisting of a gold base, a nickel diffusion barrier, and a gold-tin solder stack. Complementary structures were similarly fabricated on polyimide tapes with a thickness of 5 µm, that later served as substrates for the silicon chips. At the center of the investigation are the observed silicon deformations and their simulation based on the finite element method (FEM) and using a downsized model. Global and local deformations (that is deformations on the chip-level and bump-level, respectively) are analyzed and adapted FEM models are developed based on the simulation tool ANSYS 11.0. Because the observed deformations are a result of the process history as a whole, the mechanical stress in the electroplated layers, as well as deformations during heating and cooling of the reflow and soldering processes, were taken into account in the conception of the model. Using long lines of solder deposit in several test chips, the orientation of the deformation could be directly influenced and their magnitude could be increased, allowing the deformations to be observed and measured during the soldering process as a function of temperature and time. These data and their dependence on the silicon thickness and the solder bump geometry were used to significantly improve the model, which initially was based mostly on material data from the literature. With the improvement of the model a good agreement between simulated and measured deformations was mostly achieved. It was also shown, that the anisotropic mechanical properties of silicon dominate the orientation of the bending axis in "thick" chips, while in very thin chips the metallic structures have an increasing influence. It was also shown, that, assuming an adapted design and silicon and metal structure thicknesses, reflowed silicon chips could be fabricated without any resulting global deformation. This can significantly improve chip handling during subsequent processes