Two-Way Training for Discriminatory Channel Estimation in Wireless MIMO Systems

This work examines the use of two-way training to efficiently discriminate the channel estimation performances at a legitimate receiver (LR) and an unauthorized receiver (UR) in a multiple-input multiple-output (MIMO) wireless system. This work improves upon the original discriminatory channel estimation (DCE) scheme proposed by Chang et al where multiple stages of feedback and retraining were used. While most studies on physical layer secrecy are under the information-theoretic framework and focus directly on the data transmission phase, studies on DCE focus on the training phase and aim to provide a practical signal processing technique to discriminate between the channel estimation performances at LR and UR. A key feature of DCE designs is the insertion of artificial noise (AN) in the training signal to degrade the channel estimation performance at UR. To do so, AN must be placed in a carefully chosen subspace based on the transmitter's knowledge of LR's channel in order to minimize its effect on LR. In this paper, we adopt the idea of two-way training that allows both the transmitter and LR to send training signals to facilitate channel estimation at both ends. Both reciprocal and non-reciprocal channels are considered and a two-way DCE scheme is proposed for each scenario. {For mathematical tractability, we assume that all terminals employ the linear minimum mean square error criterion for channel estimation. Based on the mean square error (MSE) of the channel estimates at all terminals,} we formulate and solve an optimization problem where the optimal power allocation between the training signal and AN is found by minimizing the MSE of LR's channel estimate subject to a constraint on the MSE achievable at UR. Numerical results show that the proposed DCE schemes can effectively discriminate between the channel estimation and hence the data detection performances at LR and UR.Comment: 1

A Linux PC cluster for lattice QCD with exact chiral symmetry

A computational system for lattice QCD with exact chiral symmetry is described. The platform is a home-made Linux PC cluster, built with off-the-shelf components. At present this system constitutes of 64 nodes, with each node consisting of one Pentium 4 processor (1.6/2.0/2.5 GHz), one Gbyte of PC800/PC1066 RDRAM, one 40/80/120 Gbyte hard disk, and a network card. The computationally intensive parts of our program are written in SSE2 codes. The speed of this system is estimated to be 70 Gflops, and its price/performance is better than $1.0/Mflops for 64-bit (double precision) computations in quenched QCD. We discuss how to optimize its hardware and software for computing quark propagators via the overlap Dirac operator.Comment: 24 pages, LaTeX, 2 eps figures, v2:a note and references added, the version published in Int. J. Mod. Phys.

Two-way training for discriminatory channel estimation in wireless MIMO systems

This work examines the use of two-way training to efficiently discriminate the channel estimation performances at a legitimate receiver (LR) and an unauthorized receiver (UR) in a multiple-input multiple-output (MIMO) wireless system. This work improves upon the original discriminatory channel estimation (DCE) scheme proposed by Chang where multiple stages of feedback and retraining were used. While most studies on physical layer secrecy are under the information-theoretic framework and focus directly on the data transmission phase, studies on DCE focus on the training phase and aim to provide a practical signal processing technique to discriminate between the channel estimation performances (and, thus, the effective received signal qualities) at LR and UR. A key feature of DCE designs is the insertion of artificial noise (AN) in the training signal to degrade the channel estimation performance at UR. To do so, AN must be placed in a carefully chosen subspace, based on the transmitter's knowledge of LR's channel, in order to minimize its effect on LR. In this paper, we adopt the idea of two-way training that allows both the transmitter and LR to send training signals to facilitate channel estimation at both ends. Both reciprocal and nonreciprocal channels are considered and a two-way DCE scheme is proposed for each scenario. For mathematical tractability, we assume that all terminals employ the linear minimum mean square error criterion for channel estimation. Based on the mean square error (MSE) of the channel estimates at all terminals, we formulate and solve an optimization problem where the optimal power allocation between the training signal and AN is found by minimizing the MSE of LR's channel estimate subject to a constraint on the MSE achievable at UR. Numerical results show that the proposed DCE schemes can effectively discriminate between the channel estimation and, hence, the data detection performances at LR and UR.This work was supported in part by the National Science Council, Taiwan, by Grant NSC 100-2628-E-007-025-MY3 and Grant NSC 101-2218-E-011-043, and in part by the Australian Research Council's Discovery Projects Funding Scheme (Project no.DP110102548)

A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications

High Efficiency Video Coding, the latest video standard, uses larger and variable-sized coding units and longer interpolation filters than [H.264 over AVC] to better exploit redundancy in video signals. These algorithmic techniques enable a 50% decrease in bitrate at the cost of computational complexity, external memory bandwidth, and, for ASIC implementations, on-chip SRAM of the video codec. This paper describes architectural optimizations for an HEVC video decoder chip. The chip uses a two-stage subpipelining scheme to reduce on-chip SRAM by 56 kbytes-a 32% reduction. A high-throughput read-only cache combined with DRAM-latency-aware memory mapping reduces DRAM bandwidth by 67%. The chip is built for HEVC Working Draft 4 Low Complexity configuration and occupies 1.77 mm[superscript 2] in 40-nm CMOS. It performs 4K Ultra HD 30-fps video decoding at 200 MHz while consuming 1.19 [nJ over pixel] of normalized system power.Texas Instruments Incorporate

A 249Mpixel/s HEVC video-decoder chip for Quad Full HD applications

The latest video coding standard High Efficiency Video Coding (HEVC) provides 50% improvement in coding efficiency compared to H.264/AVC, to meet the rising demand for video streaming, better video quality and higher resolutions. The coding gain is achieved using more complex tools such as larger and variable-size coding units (CU) in a hierarchical structure, larger transforms and longer interpolation filters. This paper presents an integrated circuit which supports Quad Full HD (QFHD, 3840×2160) video decoding for the HEVC draft standard. It addresses new design challenges for HEVC (“H.265”) with three primary contributions: 1) a system pipelining scheme which adapts to the variable-size largest coding unit (LCU) and provides a two-stage sub-pipeline for memory optimization; 2) unified processing engines to address the hierarchical coding structure and many prediction and transform block sizes in area-efficient ways; 3) a motion compensation (MC) cache which reduces DRAM bandwidth for the LCU and meets the high throughput requirements which are due to the long filters.Texas Instruments Incorporate

A computational system for lattice QCD with overlap Dirac quarks

We outline the essential features of a Linux PC cluster which is now being developed at National Taiwan University, and discuss how to optimize its hardware and software for lattice QCD with overlap Dirac quarks. At present, the cluster constitutes of 30 nodes, with each node consisting of one Pentium 4 processor (1.6/2.0 GHz), one Gbyte of PC800 RDRAM, one 40/80 Gbyte hard disk, and a network card. The speed of this system is estimated to be 30 Gflops, and its price/performance ratio is better than $1.0/Mflops for 64-bit (double precision) computations in quenched lattice QCD with overlap Dirac quarks.Comment: 3 pages, Lattice 2002(machine

Implementation of Intelligent Green Energy Management System

In this work, we mainly apply the cloud infrastructure (IaaS) and virtualization technology to provide the construction services of a green energy management system. First of all, we used MySQL Cluster database technology to build a data storage system which can solve the challenge of large demand. Digital electricity meter data and environmental information are collected efficiently and quickly in the proposed green energy management system. Next, a virtualized user-interface is provided by graphical presentation to facilitate data analysis. Finally, we control the electricity equipment to reduce Power Usage Effectiveness (PUE) and the overall power consumption target-based on this virtualized user-interface of the data analysis