A high-energy ion implanted BICMOS process with compatible EPROM structures

A 1.5µm high-energy ion implanted BiCMOS process is proposed. This process offers NMOS, PMOS, vertical npn transistors and VIPMOS-EPROM devices. The process structure is modular in order to achieve CMOS and bipolar transistors in uncompromised forms. Consequently, the N-well and collector regions are defined separately. Conflicting requirements for the collector doping profile have been optimized towards practical electrical device characteristics

TASTE: a tool for analog system testability evaluation

A method is presented to analyze the testability of both linear and nonlinear analog systems. It combines a rank-test algorithm with statistical methods. The algorithm finds sets of inseparable parameters and determines whether it is possible to calculate a certain parameter with efficient accuracy. It also determines a subset of appropriate measurements if redundant measurements are presen

Modeling of VIPMOS hot electron gate currents

A buried injector, which is biased by means of punch-through, can be used in substrate hot electron injection EEPROM devices [1]. In order to optimize this device an empirical expression for the injection probability as a function of the effective barrier height and the average electron energy is proposed and verified by measurements on a variety of devices

VIPMOS, a buried local injector for EPROMs

A highly effective substrate hot electron injection EPROM device can be made using a buried injector, which operates in punch-through mode. The buried injector is formed by a local overlap of the N-well and P-well of a retrograde twin-well CMOS-process. As the VIPMOS-EPROM is compatible with VLSI-processing and the danger of latch-up doesn't exist, the VIPMOS-structure may be used in VLSI-applications. Due to an efficient electron supply mechanism as well as a high injection probability, programming rates of 1V/μs can be obtained