A 1.5µm high-energy ion implanted BiCMOS process is proposed. This process offers NMOS, PMOS, vertical npn transistors and VIPMOS-EPROM devices. The process structure is modular in order to achieve CMOS and bipolar transistors in uncompromised forms. Consequently, the N-well and collector regions are defined separately. Conflicting requirements for the collector doping profile have been optimized towards practical electrical device characteristics

Hemink, G.J.

Hemink, Gertjan

Middelhoek, J.

Wallinga, Hans

Wijburg, R.C.M.

Wallinga, H.

University of Twente Research Information

Papa pusanat al ESSDERi 90 \ i ^ { t %it , } ¡a 1990 515Se SWi»î \ 1A high-energ) ¡on implanted BICMOS process with compatible EPROMstructuresRCM Wijburg, G J Hemink, J Middelhoek and H WalungaUniversity of Twente, sabdepartment IC-technology and ElectronicsEO. box 21% 7500AE Enschede (NL)Abstract. A 1.5pm high-energy ion implanted BÏCMOS process is proposed. Thisprocess offers NMOS, PMOS, vertical npn transistors and VIPMOS-EPROMdevices. The process structure is modular in order to achieve CMOS and bipolartransistors io uncompromised forms. Consequently, the Newell and collectorregions are defined separately. Conflicting requirements for the collector dopingprofile have been optimized towards practical electrical device characteristics,1. IntroductionIn general BiCMOS processes employ epitaxy combined with buried layers to ensure lowcollector and well resistances. A promising alternative is offered by high-energy ionimplantation. The high-energy collector or well implantation can be performed in a self-aligned way to the field oxide, thereby making area-consuming stopper implantations andburied layers superfluous. Besides giving process simplifications, ion implantation enables agood reproducibility by its precise control over the implanted dose and energy.In a First proposal to use high energy ion implantation in BiCMOS processing, Volz andBlossfeld (1988) have reported a technology in which the N-well for the P-channel device isto be shared with the collector for the bipolar device. The N-well and collector, however, dohave conflicting implantation requirements. Therefore, the N-well and collectorimplantations should be separated to reap the full benefit of the BiCMOS technology.2. Process StructureThe developed BiCMOS process has a modular structure, which is settled in a CMOS, abipolar and an EPROM part. A beneficial result, achieved by the modular approach, is thatthe process parts can be optimized individually without severely affecting other parts. TheCMOS process, proposed by Stolmeijer (1986), forms the basic part. It covers thefabrication of n-channel and p-channel MOS devices. The bipolar part leads to therealization of a vertical npn transistor with polysiiicon emitter. The EPROM part makesthe ipplication of VIPMOS-EPROM's (Wijburg er al, (1989)) for integrated circuit designpossible. The acronym VIPMOS stands for Vertical Injection Punch-through-based MOS.High-energy ion implantation is a key-tech nique for the realization of each of these threeparts. A schematic cross-section of the process is shown in figure 1. The retrograde N-well1990 ¡OP P nlislui Ï J516 ESSDERC90wmm-EmmiFig. 1 A schematic cross-section of the high-energy ion implanted BiCMOS process.Active Area DefinitionLOCOS Growthand P-well are implanted with 1 MeV phosphorus and 350 keV boron ions, respectively. Theinjector of the VIPMOS-EPROM is made by a local overlap of the P-well and N-well. 1.5MeV phosphorus ions are implanted to form the collector.Featuring two polysilicon layers and one metal layer, the total number of masks used is 14.The realization of bipolar transistor involves three extra masks compared to the 10 masksfor the basic process. Only one additional mask is needed for the VIPMOS-EPROM, inorder to counter-dope trunks from the buried injector up to the surface (Wijburg ei al.(1990)). A process flow is illustrated in Figure 2. The retrograde P-well and N-well areimplanted after the LOCOS growth. A PT-masked (Preventing Trunk) boron implantation,covering all the injector edges in active area, is carried out to prevent short-circuits betweenthe injector and channel. Then the gate oxide is grown. The first polysilicon layer providesthe gates of normal CMOS devices as well as thefloating gate of the EPROM. After the gateformation, the base and collector are implanted.Subsequently, an emitter window is opened in thegate-oxide. The polysilicon emitter and controlgate for the EPROM are defined with a secondpolysilicon layer. An implanted collector plugensures a low-ohmic connection between thecollector and its metallic contact The source anddrain of the normal MOS devices employ DDD-structures. Because of the use of the SubstrateHot Electron (SHE) injection technique, theVIPMOS-EPROM can use the same advancedsource and drain structures. The source/drainimplantations for the PMOS device are used forthe base contact, whereas the source/drainimplantations for the NMOS device are employedfor the collector contact.TN-well &. P-wellFormationTPreventing TrunkTPolysiliconGate FormationTBase, Collector &Emitter DefinitionTCMOSBipolarEPROMCMOSEPROMEPROMCMOSEPROMBipolarSecond PolysiliconFormation-J-BipolarEPROMCollector PlugTBipolar 3. Collector OptimizationSource, Drain, Base &.Collector ContactTMetallizationCMOSBipolarEPROMCMOSBipolarEPROMFig. 2 The process flow.Since even high-energy ion implantation covers arestricted depth, the use of a polysilicon emitteroffers profitable space in the vertical direction.Notwithstanding the very shallow emitter-basejunction, there are conflicting collector require¬ments. This is illustrated in Figure 3. It comparesSilicon tuants 517the ID-doping profile, as simulated withSUPREM IUf and that extracted from SIMSmeasurements. The collector was realized bymeans of a 1.5 MeV phosphorus implantation. Adotted line separates the collector in two virtualregions.On one hand the collector doping concentrationin region I should be low because of parameterssuch as the collector-emitter breakdown voltageVceo* the collector-base junction capacitanceQb, and the Early-voltage VA. On the otherhand the doping concentration in region IIshould be high, in order to achieve a low col¬lector resistance R^ Unfortunately, the dopingconcentration in the collector regions I and IIcannot be chosen independently. The above-mentioned problem is aggravated by thedemand of a sufficient high doping concentra¬tion underneath the LOCOS to avoid possibleparasitic MOS-action. These issues are ad¬dressed in Figure 4. V^mp is defined as thecollector-emitter voltage V^, at which the increased collector current, generated throughimpact ionization in the collector-base space charge region, causes a 25 % decrease of thebase current Vth is the threshold voltage of parasitic MOS transistor underneath the 600nm thick LOCOS.Aiming at a 5 V supply voltage, it can be concluded from Figure 4 that the 1 MeVimplantation hardly suffices. In the case of a 1.5 MeV implantation, the allowable collectordose ranges from about 2x10 to 5x10 cm . The lower limit is determined by thethreshold voltage of the parasitic MOS transistor; the upper limit by impact ionization. As aresult, the minimum achievable collector sheet resistivity is 290O/D.Fig. 3 Typical simulated (dashed) andmeasured (solid) ID-doping profiles ofthe npñ transistor.Fig, 4 Parameters of thenpn transistor, consideredfor the collector optimiza¬tion^ as a function of thecollector dose. The dopingspecies is phosphorus.(A) 1 MeV simulated;(O) 15 MeV simulated;(%) 1,5 MeV measured.518 ESSDEEC 904. Device CharacteristicsTable 1 shows the main parameters of the normal MOS devices and the opn transistor witha maximum collector dose. In Figure 5 the corresponding Gummel plot is displayed. Thecollector and base current exhibit an ideal behaviour. The current gain is 100 and nearlyconstant over 6 decades. Cut-off frequencies as high as 6 GHz have been measured.(20/20) NMOS PMOSVth (V)Y (v1/2)S (mV/dec)BVDSSCV)0.700.5988»10"0.720.5882>10NPNBetaVA (V)fxm« (GHz)V^ (V)Vefao (V)100306.0 (Veb=4 V)6.78.6Table I Device parameters.5. ConclusionsIC IB< A) CURSOR < ,8000V , 274. 3nA , 268. 8nA ) C A).HARKER < .6000V . 274. 3nA . 2. 87*nA )Pig. 5 Gummel plot of the optimizednpn transistor (AE is 5x5pm ).A 1.5 pm high energy ion implanted BiCMOS process has been proposed. This processrelies on the modular adding of bipolar and EPROM structures to an existing retrogradetwin-well CMOS process. It demonstrates the versatility of high-energy ion implantation.Using a polysilicon emitter and a separate collector implantation, the collector dopingprofile has been optimized. The optimization problem has been discussed in greater depthfor the implantation energy range 1-1.5 MeV.AcknowledgmentsThe authors appreciate the assistance of Dr. van der Vlist during the high frequencymeasurements. They thank G. Boom and A. Kooy for their skilful processing. This workwas supported by the Found?tion for Fundamental Research on Matter (FOM) and theNetherlands Technology Foundation (STW).ReferencesStolmeijer A 1986 IEEE Trans, Electron Devices ED-33 pp 450-457Volz C and Blossfeld L 1988 IEEE Trans. Electron Devices ED-35 pp 1861-1865Wijburg RCM, Hemink G J, Praamsma L and Middelhoek J 1989 Proc. ESSDERC pp915-918Wijburg RCM, Hemink G J and Middelhoek J 1990 IEEE Trans. Electron Devices EDT37pp 79-87

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A high energy ion implanted BiCMOS process with compatible EPROM structures

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A high-energy ion implanted BICMOS process with compatible EPROM structures

A high-energy ion implanted BICMOS process with compatible EPROM structures

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