Building an Application-specific Memory Hierarchy on FPGA

The high potential performance of FPGAs cannot be exploited if a design suffers a memory bottleneck. Therefore, a memory hierarchy is needed to reuse data in on-chip memories and minimize the number of accesses to off-chip memory

Optimizing the FPGA memory design for a Sobel edge detector

This paper explores different memory systems by investigating the trade-offs involved with choosing one memory system over another on an FPGA. As an example, we use a Sobel edge detector to look at the trade-offs for different memory components. We demonstrate how each type of memory affects I/O performance and area. By exploiting these trade-offs in performance and area a designer should be able to find an optimum on-chip memory system for a given application

Finding Bounds on Ehrhart Quasi-Polynomials

C

Reducing the dynamic FPGA reconfiguration overhead

Dynamic hardware generation reduces the number of FPGA resources needed and speeds up the application by optimizing the configuration for the exact problem at hand at run-time. If the problem changes, the system needs to be reconfigured. When this occurs too often, the total reconfiguration overhead is too high and the benefit of using dynamic hardware generation vanishes. Hence, it is important to minimize the number of reconfigurations

An exploration of synchronization solutions for parallel short-range optical interconnect in mesochronous systems

As a result of the increasing complexity of electronic chips, the bandwidths required for inter- and intra-chip communication are rapidly increasing. As optoelectronics provides high=bandwidth and high-density interconnection it is considered as a candidate for short-range interconnection. For such interconnections, situated at a low level in the systems hierarchy, the interconnect latency is extremely critical for the systems performance. This paper describes some methods for mesochronous synchronization, needed for such interconnections. It will be shown that it can be beneficial to use an additional optical link to transfer a synchronization signal. Such a reference signal can be used efficiently for phase detection, provided that the data skew is sufficiently small, and result in a decrease of the cost-per-link

CLooGVHDL and JCCI

CLooGVHDL and JCCI offer an extendible C-to-VHDL framework to develop high-level synthesis techniques for data-intensive applications on heterogeneous memory systems. 1