Improvement of channel-carrier mobility in 4H-SiC MOSFETs correlated with passivation of very fast interface traps using sodium enhanced oxidation

Very fast interface traps have recently been suggested to be the main cause behind the rather poor inversion channel mobility in nitrided SiC metal-oxide-semiconductor-field-effect-transistors (MOSFETs). Using capacitance voltage analysis and conductance spectroscopy on metal oxide semiconductor capacitors, at cryogenic temperatures, we find that these fast traps are absent in oxides made by sodium enhanced oxidation, and high inversion channel-carrier mobility in MOSFETs made by sodium enhanced oxidation is observed.Funding Agencies|Icelandic Center for Research (Rannis) [185412-052]; University of Iceland Research Fund</p

Electrically Active Defects in SiC Power MOSFETs

The performance and reliability of the state-of-the-art power 4H-SiC metal&ndash;oxide&ndash;semiconductor field-effect transistors (MOSFETs) are affected by electrically active defects at and near the interface between SiC and the gate dielectric. Specifically, these defects impact the channel-carrier mobility and threshold voltage of SiC MOSFETs, depending on their physical location and energy levels. To characterize these defects, techniques have evolved from those used for Si devices to techniques exclusively designed for the SiC MOS structure and SiC MOSFETs. This paper reviews the electrically active defects at and near the interface between SiC and the gate dielectric in SiC power MOSFETs and MOS capacitors. First, the defects are classified according to their physical locations and energy positions into (1) interface traps, (2) near interface traps with energy levels aligned to the energy gap, and (3) near-interface traps with energy levels aligned to the conduction band of SiC. Then, representative published results are shown and discussed for each class of defect

Electrically Active Defects in SiC Power MOSFETs

The performance and reliability of the state-of-the-art power 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) are affected by electrically active defects at and near the interface between SiC and the gate dielectric. Specifically, these defects impact the channel-carrier mobility and threshold voltage of SiC MOSFETs, depending on their physical location and energy levels. To characterize these defects, techniques have evolved from those used for Si devices to techniques exclusively designed for the SiC MOS structure and SiC MOSFETs. This paper reviews the electrically active defects at and near the interface between SiC and the gate dielectric in SiC power MOSFETs and MOS capacitors. First, the defects are classified according to their physical locations and energy positions into (1) interface traps, (2) near interface traps with energy levels aligned to the energy gap, and (3) near-interface traps with energy levels aligned to the conduction band of SiC. Then, representative published results are shown and discussed for each class of defect

A Figure of Merit for Selection of the Best Family of SiC Power MOSFETs

This paper proposes a criterion to select the best family of commercial SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs) that provides the highest quality and reliability. Applying a recently published integrated-charge method, a newly proposed figure of merit is correlated to the density of near-interface traps that degrade the quality and reliability of SiC MOSFETs. The applicability of the proposed figure of merit is experimentally demonstrated with the most widely used and commercially available planar and trench MOSFETs from different manufacturers

Detection of near-interface traps in NO annealed 4H-SiC metal oxide semiconductor capacitors combining different electrical characterization methods

Fast near-interface (NI) traps have recently been suggested to be the main cause for poor inversion channel mobility in nitrided SiC metal-oxide-semiconductor-field-effect-transistors. Combining capacitance, conductance, and thermal dielectric relaxation current (TDRC) analysis at low temperatures of nitrided SiC MOS capacitors, we observe two categories of fast and slow near-interface traps at the SiO2/4H-SiC interface. TDRC reveals a suppression of slow near-interface traps after nitridation. Capacitance and conductance analysis reveals a high density of fast NI traps close to the SiC conduction band edge that are enhanced by nitridation. The very fast response of NI traps prevents them from detection using TDRC or deep level transient spectroscopy. (C) 2022 Author(s).Funding Agencies|Icelandic Centre for Research (Rannis) [185412-052]; University of Iceland Research Fund</p