150°C amorphous silicon thin-film transistor technology for polyimide substrates

We have developed a 150°C technology for amorphous silicon thin-film transistors (a-Si:H TFTs) on polyimide substrates deposited by plasma enhanced chemical vapor deposition. The silicon nitride gate dielectric and the a-Si:H channel material were tailored to provide the least leakage current and midgap defect density, respectively. In addition, we conducted experiments on the TFT structure and fabrication with the aim of obtaining high electron mobility. TFTs with back-channel etch and channel-passivated structures were fabricated on glass or 51 μm thick polyimide foil. The a-Si:H TFTs have an on/off current ratio of ∼10 7 and an electron mobility of ∼0.7 cm 2/V s

Electronic properties of very thin native SiO2/a-Si:H interfaces and their comparison with those prepared by both dielectric barrier discharge oxidation at atmospheric pressure and by chemical oxidation

The contribution deals with electronic properties of thin oxide/amorphous hydrogenated silicon (a-Si:H) measured by capacitance-voltage (C-V) and charge version of deep level transient spectroscopy (Q-DLTS). The interest was focused on the studies of the interface properties of very thin dielectrics formed by dielectric barrier discharge (DBD) or natively on the a-Si:H layer. These properties were compared with those of oxide layers prepared by chemical oxidation in HNO3. The DBD was used for the preparation of a very thin SiO2 layer on a-Si:H for the first time to our knowledge. Preliminary electrical measurements confirmed that a very low interface states density was detected in the case of the native oxide/a-Si:H and DBD oxide/a-Si:H

Mechanical theory of the film-on-substrate-foil structure : curvature and overlay alignment in amorphous silicon thin-film devices fabricated on free-standing foil substrates

Flexible electronics will have inorganic devices grown at elevated temperatures on free-standing foil substrates. The thermal contraction mismatch between the substrate and the deposited device films, and the built-in stresses in these films, cause curving and a change in the in-plane dimensions of the workpiece. This change causes misalignment between the device layers. The thinner and more compliant the substrate, the larger the curvature and the misalignment. We model this situation with the theory of a bimetallic strip, which suggests that the misalignment can be minimized by tailoring the built-in stress introduced during film growth. Amorphous silicon thin-film transistors (a-Si:H TFTs) fabricated on stainless steel or polyimide (PI) (Kapton E®) foils need tensile built-in stress to compensate for the differential thermal contraction between the silicon films and the substrate. Experiments show that by varying the built-in stress in just one device layer, the gate silicon nitride (SiNx), one can reduce the misalignment between the source/drain and the gate levels from ∼400 parts-per-million to ∼100 parts-per-million

Electrophotographically printed insulator

Because the toners for electrophotographic (laser) printing are based on electrically insulating organic polymers, digitally controlled patterned insulator layers can be printed directly. We fabricated Cr/printed-insulator/Cr capacitors with 10-μm- or 25-μm-thick laser-printed commercial toner layers as the dielectric between Cr electrodes. The capacitors had leakage currents of ∼1 nA/cm2 at the voltage of 100 V. The resistivity of the printed toner layer was ∼1013 Ω cm, the dielectric breakdown field ≥5×104 V/cm, and the dielectric constant ∼3

a-Si:H TFTs on polyimide foil : electrical performance under mechanical strain

This paper looks at a-Si:H TFTs on polyimide foil: electrical performance under mechanical strai

Fabrication of thin-film transistors on polyimide foils

This chapter looks at fabrication of thin-film transistors on polyimide foil

a-Si:H thin film transistors after very high strain

We fabricate amorphous silicon (a-Si:H) thin-film transistors (TFTs) on a 25 μm Kapton foil, and then bend the foil over mandrels of various radii. The bending causes tensile strain in the TFTs when they face out, and compressive strain when they face in. After bending, we measure the electrical properties of the TFTs. After ∼2% of compressive strain, there is no change in the TFT electrical performance due to bending, namely in the on-current, off-current, source-gate leakage current, mobility and the threshold voltage. In tension, no change in the TFT performance is observed up to the strain of ∼0.5%. For larger tensile strains TFTs fail mechanically by cracking of the TFT layers. These cracks run perpendicularly to the bending direction

Ozone oxidation methods for aluminium oxide formation : application to low-voltage organic transistors

Four atmospheric pressure ozone oxidation methods were used to produce ultra-thin layers of aluminium oxide for organic thin-film transistors. They are UV/ozone oxidation in ambient (UV-AA) and dry (UV-DA) air, UV/ozone oxidation combined with high-voltage discharge-generated ozone in dry air (UV+O3-DA), and discharge-generated ozone in dry air (O3-DA). The lack of the high-energy UV photons during the O3-DA oxidation led to low relative permittivity and high leakage current density of the AlOx layer that rendered this method unsuitable for transistor dielectrics. Although this oxidation method led to the incorporation of oxygen into the film, the FTIR confirmed an increased concentration of the subsurface oxygen while the XPS showed the highest portion of the unoxidized Al among all four methods. The remaining three oxidation methods produced AlOx films with thicknesses in excess of 7 nm (2-hour oxidation time), relative permittivity between 6.61 and 7.25, and leakage current density of (1-7)x10-7 A/cm2 at 2 MV/cm, and were successfully implemented into organic thin-film transistors based on pentacene and DNTT. The presence of –OH groups in all oxides is below the detection limit, while some carbon impurities appear to be incorporated