Design of High Performance Quaternary Adders

Design of the binary logic circuits is limited by the requirement of the interconnections. A possible solution could be arrived at by using a larger set of signals over the same chip area. Multiple-valued logic (MVL) designs are gaining importance from that perspective. This paper presents two types of multiple-valued full adder circuits, implemented in Multiple-Valued voltage-Mode Logic (MV-VML). First type is designed using one hot encoding and barrel shifter. Second full adder circuit is designed by converting the quaternary logic in to unique code, which enables to implement circuit with reduced hard ware. Sum and carry are processed in two separate blocks, controlled by code generator unit. The design is targeted for the 0.18 μm CMOS technology and verification of the design is done through Synopsis HSPICE and COSMOSCOPE Tools. Area of the designed circuits is less than the corresponding binary circuits and quaternary adders because number of transistors used are less

Load Balancing in Multi ECU Configuration

Electronic Control Units (ECUs) are widely used to improve the comfort and reliability of vehicles. It has become the fundamental building block of any automotive subsystem and is interfaced with electro mechanics counterpart. To meet the system wide requirements, these ECUs are interconnected using the communication infrastructure. Although the communication infrastructure in terms of, predominantly, the CAN based vehicle network took its birth to enable ECUs to work in a coordinated manner in order to support system wide requirements, during the past decade, this infrastructure was also viewed as a potential means to incorporate extensibility in terms of addition of newer ECUs which are built for implementing additional requirements. With this paradigm, the number of ECUs started growing in a steep manner, uncontrolled and as a result, today, it is not hard to see a high segment automotive housing ECUs as large as 75-80. Hence, load balancing mechanisms are needed to ease ECU integration and for efficient utilization of CPU power in ECUs. In this paper, we explain the mathematical approach for load balancing across ECUs on the basis of CPU utilization

Artificial neural networks as building blocks of mixed signal FPGA

Ever since the deployment of FPAAs, efforts are on the way to minimize the silicon area to realize an arbitrary system. A relatively new concept which has been tested and tried in this direction is the use of Artificial neural networks (ANNs) as Configurable Analog Blocks (CABs). Conventional ANNs however suffer with lengthy training period. In this paper ANNs with differential feedback technique are explored. It has been found out that they perform better than the conventional ANNs

Load Balancing towards ECU Integration

There has been an exponential increase in the number of electronic components embedded in vehicles. Development processes, techniques and tools have changed to accommodate that evaluation. A wide range of electronic functions such as navigation, adaptive control, infotainment, traffic information, safety system etc are implemented in today’s vehicles. Many of the new functions are not stand alone and hence they need to exchange information, sometimes with stringent time constraints for time critical functions such as engine management, collision warning systems etc. The complexity of the embedded architecture in a vehicle is continually increasing. Today up to 2500 signals are exchanged through up to 70 Electronic Control Units (ECUs) using 5 different buses. This paper introduces the load balancing approach across ECUs supplied by various Tier1 suppliers

Fast and power efficient 16×16 Array of Array multiplier using Vedic Multiplication

This paper discusses about "Array of Array" multiplier which is a derivative of Braun Array Multiplier. Braun array are much suitable for VLSI implementation because of its less space complexity though it shows larger time complexity, on the other hand tree multipliers have time complexity of O(log n) but are less suitable for VLSI implementation since, being less regular; they require larger total routing length, which leads to performance degradation; simply put, they show higher space complexity. The main advantage of "Array of Array" multipliers is its inherent ability to reduce both time and space complexity [7] [8] with intermediate relative performance [7]. In this paper a 16×16 unsigned 'Array of Array' multiplier circuit is designed with hierarchical structuring, it has been optimized using Vedic Multiplication Sutra (Algorithm) "Urdhva Triyagbhyam" [1][6] and Karatsuba-Ofman algorithm[2]. The proposed algorithm is useful for math coprocessors in the field of computers. Algorithm is implemented on SPARTAN-3E FPGA (Field Programmable Gate Array). The proposed multiplier implementation shows large reduction in average power dissipation and in time delay as compared to Booth encoded radix-4 multiplier

Load balancing issues in automotives

Electronic Control Units (ECUs) are widely used to improve the comfort and reliability of vehicles. It has become the fundamental building block of any automotive subsystem and is interfaced with electro mechanics counterpart. To meet the system wide requirements, these ECUs are interconnected using the communication infrastructure. Although the communication infrastructure in terms of, predominantly, the CAN based vehicle network took its birth to enable ECUs to work in a coordinated manner in order to support system wide requirements, during the past decade, this infrastructure was also viewed as a potential means to incorporate extensibility in terms of addition of newer ECUs which are built for implementing additional requirements. With this paradigm, the number of ECUs started growing in a steep manner, uncontrolled and as a result, today, it is not hard to see a high segment automotive housing ECUs as large as 75–80. Hence, load balancing mechanisms are needed to ease ECU integration and for efficient utilization of CPU power in ECUs. In this paper, we explain the concept of load balancing on the basis of CPU utilization across ECUs

Information geometry of differentially fed artificial neural networks

A new class of neural networks with differential feedback are presented. The different orders of differential feedback form a manifold of hyperplanes, one among them called eigen-plane corresponding to /spl infin/ order feedback. In this paper information geometry is used to explore the interesting properties of this plane

Design and Implementation of Integer Transform and Quantization Processor for H.264 Encoder on FPGA

This paper proposes a novel implementation of the core processors, the integer transform and quantization for H.264 video encoder using an FPGA. It is capable of processing the picture frames with the desired compression controlled by the user input. The algorithm and architecture of the components of the video encoder namely, integer transformation, quantization were developed, designed and coded in Verilog. The complete H.264 video encoder was coded in Matlab in order to verify the results of the Verilog implementation. The processor is implemented on a Xilinx Vertex – II Pro XC2VP30 FPGA. The gate count of the implementation is approximately 1,057,000 working at a frequency of 208 MHz. It can process 1024x768 pixel color images in 4:2:0 format at 25 frames per second. The reconstructed picture quality is better than 35 dB

Investigation and modeling on protective textiles using artificial neural networks for defense applications

Kevlar 29 is a class of Kevlar fiber used for protective applications primarily by the military and law enforcement agencies for bullet resistant vests, hence for these reasons military has found that armors reinforced with Kevlar 29 multilayer fabrics which offer 25–40% better fragmentation resistance and provide better fit with greater comfort. The objective of this study is to investigate and develop an artificial neural network model for analyzing the performance of ballistic fabrics made from Kevlar 29 single layer fabrics using their material properties as inputs. Data from fragment simulation projectile (FSP) ballistic penetration measurements at 244 m/s has been used to demonstrate the modeling aspects of artificial neural networks. The neural network models demonstrated in this paper is based on back propagation (BP) algorithm which is inbuilt in MATLAB 7.1 software and is used for studies in science, technology and engineering. In the present research, comparisons are also made between the measured values of samples selected for building the neural network model and network predicted results. The analysis of the results for network predicted and experimental samples used in this study showed similarity

Studies on buried layer resistors

Multilayer thick-film technology is one of the important technologies adopted in the miniaturization of electronic systems. Generally, only interconnections are made in the intermediate layers. The possibility of fabricating resistors along with interconnections in the buried layers/intermediate layers using conventional thick-film materials has been examined in this study. The fabrication has been carried out by processing layer after layer. It has been found that the buried layer resistors exhibited a sheet resistivity lower than those fabricated as open resistors. This change in sheet resistivity has been attributed to multiple firings that the resistors undergo during the fabrication. This reduction in sheet resistivity has been found to be due to segregation of active materials. A model has been proposed to explain this change in sheet resistivity through segregation of the active material. The work reported in the paper clearly indicates that buried resistors with consistent values (+/-10%) can be fabricated using conventional materials. However, the design of the resistors has to be carried out using modified sheet resistivities. The model that is proposed also indicates how one can make a paste that is likely to exhibit the same sheet resistivity for buried resistors and open resistors. (C) 2002 Kluwer Academic Publishers