Comparator hysteresis compensation for decision feedback equalisers

High-speed comparators are extensively used in serial link receiver designs. Some comparator architectures can show significant hysteresis that degrade the sensitivity of the receiver, increasing the bit error rate. In this Letter, a comparator hysteresis compensation strategy that re-uses the first tap of a decision feedback equaliser to shift the comparator input voltage, increasing the decision margin is proposed. An updated equaliser coefficient adaptation scheme is also introduced. The proposed technique can be used for binary and multi-level modulations

An up to 36Gbps analog baseband equalizer and demodulator for mm-wave wireless communication in 28nm CMOS

P

Vega: A Ten-Core SoC for IoT Endnodes with DNN Acceleration and Cognitive Wake-Up from MRAM-Based State-Retentive Sleep Mode

The Internet-of-Things (IoT) requires endnodes with ultra-low-power always-on capability for a long battery lifetime, as well as high performance, energy efficiency, and extreme flexibility to deal with complex and fast-evolving near-sensor analytics algorithms (NSAAs). We present Vega, an IoT endnode system on chip (SoC) capable of scaling from a 1.7- μW fully retentive cognitive sleep mode up to 32.2-GOPS (at 49.4 mW) peak performance on NSAAs, including mobile deep neural network (DNN) inference, exploiting 1.6 MB of state-retentive SRAM, and 4 MB of non-volatile magnetoresistive random access memory (MRAM). To meet the performance and flexibility requirements of NSAAs, the SoC features ten RISC-V cores: one core for SoC and IO management and a nine-core cluster supporting multi-precision single instruction multiple data (SIMD) integer and floating-point (FP) computation. Vega achieves the state-of-the-art (SoA)-leading efficiency of 615 GOPS/W on 8-bit INT computation (boosted to 1.3 TOPS/W for 8-bit DNN inference with hardware acceleration). On FP computation, it achieves the SoA-leading efficiency of 79 and 129 GFLOPS/W on 32- and 16-bit FP, respectively. Two programmable machine learning (ML) accelerators boost energy efficiency in cognitive sleep and active states

A 0.75-2.2 GHz continuously tunable quadrature VCO

none4A quadrature VCO with +/- 50% tuning continuous tuning range is presented. It is based on a core LC-QVCO with +/- 20% tuning range, a single sideband mixer, two frequency dividers and a multiplexer. The circuit has been implemented in a 0.13 um 1.2 V CMOS technology. The additional area with respect to the core LC-QVCO is 100x100 um. Quadrature error is less than 2°; the phase noise is less than -120 dBc/Hz @ 1 MHz offset over the whole tuning range and is mainly due to the LC-QVCO. Spurs are more than 34 dB below the fundamental in the worst case.mixedD. Guermandi; P. Tortori; E. Franchi Scarselli; A. GnudiD. Guermandi; P. Tortori; E. Franchi Scarselli; A. Gnud

An 11.5% Frequency Tuning, -184 dBc/Hz Noise FOM 54 GHz VCO

This work presents a robust, low area, spectral pure 65 nm VCO for mm-wave applications. The varactor, an inversion mode MOS, takes advantage of the minimum feature provided by the technology to optimize capacitance tuning range and Q. The inductor is a 1 turn spiral. A combination of digital and analog tuning is chosen to lower VCO gain. Prototypes show the following measured results: 11.5% frequency tuning range around 54 GHz, phase noise at 10 MHz of -116 dBc/Hz and -122 dBc/Hz maximumand minimum in band, respectively. Power consumption is 7.2 mW

A 0.83-2.5 GHz Continuously Tunable Quadrature VCO

A quadrature VCO with +/- 50% tuning continuous tuning range is presented. It is based on a core LC-QVCO with +/- 20% tuning range, a single sideband mixer, two frequency dividers and a multiplexer. The circuit has been implemented in a 0.13 um 1.2 V CMOS technology. The additional area with respect to the core LC-QVCO is 100x100 um. Quadrature error is less than 2\ub0; the phase noise is less than -120 dBc/Hz @ 1 MHz offset over the whole tuning range and is mainly due to the LC-QVCO. Spurs are more than 34 dB below the fundamental in the worst case

Quadrature VCOs based on direct second harmonic locking: theoretical analysis and experimental validation

We propose a theoretical analysis of the class of quadrature VCOs (QVCOs) based on two LC-oscillators directly coupled by means of the second harmonic. The analysis provides the conditions for the existence and stability of steady-state quadrature oscillations and a simplified model for the phase noise (PN) transfer function with respect to a noise source in parallel to the tank. We show that the figure of merit defined as the product between PN and current equals that of the single VCO, confirming that quadrature generation is achieved by this class of QVCO without degrading that figure of merit. An analytical model for the phase quadrature error due to tank mismatches is also proposed. The validity of all analytical models is discussed against numerical simulations. A practical implementation at 3.26 GHz with \ub120% tuning range in a 0.13um CMOS technology is also presented, confirming the main theoretical findings