Monolithic Active Pixel Matrix with Binary Counters (MAMBO) ASIC

Monolithic Active Matrix with Binary Counters (MAMBO) is a counting ASIC designed for detecting and measuring low energy X-rays from 6-12 keV. Each pixel contains analogue functionality implemented with a charge preamplifier, CR-RC{sup 2} shaper and a baseline restorer. It also contains a window comparator which can be trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit ripple counter which is reconfigured as a shift register to serially output the data from the entire ASIC. Each pixel can be tested individually. Two diverse approaches have been used to prevent coupling between the detector and electronics in MAMBO III and MAMBO IV. MAMBO III is a 3D ASIC, the bottom ASIC consists of diodes which are connected to the top ASIC using {mu}-bump bonds. The detector is decoupled from the electronics by physically separating them on two tiers and using several metal layers as a shield. MAMBO IV is a monolithic structure which uses a nested well approach to isolate the detector from the electronics. The ASICs are being fabricated using the SOI 0.2 {micro}m OKI process, MAMBO III is 3D bonded at T-Micro and MAMBO IV nested well structure was developed in collaboration between OKI and Fermilab

A vertically integrated pixel readout device for the Vertex Detector at the International Linear Collider

3D-Integrated Circuit technology enables higher densities of electronic circuitry per unit area without the use of nanoscale processes. It is advantageous for mixed mode design with precise analog circuitry because processes with conservative feature sizes typically present lower process dispersions and tolerate higher power supply voltages, resulting in larger separation of a signal from the noise floor. Heterogeneous wafers (different foundries or different process families) may be combined with some 3D integration methods, leading to the optimization of each tier in the 3D stack. Tracking and vertexing in future High-Energy Physics (HEP) experiments involves construction of detectors composed of up to a few billions of channels. Readout electronics must record the position and time of each measurement with the highest achievable precision. This paper reviews a prototype of the first 3D readout chip for HEP, designed for a vertex detector at the International Linear Collider. The prototype features 20 x 20 {micro}m{sup 2} pixels, laid out in an array of 64 x 64 elements and was fabricated in a 3-tier 0.18 {micro}m Fully Depleted SOI CMOS process at MIT-Lincoln Laboratory. The tests showed correct functional operation of the structure. The chip performs a zero-suppressed readout. Successive submissions are planned in a commercial 3D bulk 0.13 {micro}m CMOS process to overcome some of the disadvantages of an FDSOI process

Vertically integrated pixel readout chip for high energy physics

We report on the development of the vertex detector pixel readout chips based on multi-tier vertically integrated electronics for the International Linear Collider. Some testing results of the VIP2a prototype are presented. The chip is the second iteration of the silicon implementation of the prototype, data-pushed concept of the readout developed at Fermilab. The device was fabricated in the 3D MIT-LL 0.15 {micro}m fully depleted SOI process. The prototype is a three-tier design, featuring 30 x 30 {micro}m{sup 2} pixels, laid out in an array of 48 x 48 pixels

Développement d'un capteur de nouvelle génération et son électronique intégrée pour les collisionneurs futurs

Vertex detectors are of great importance in particle physics experiments, as the knowledge of the event flavour is becoming an issue for the physics programme at Future Linear Colliders. Monolithic Active Pixel Sensors (MAPS) based on a novel detector structure have been proposed. Their fabrication is compatible with a standard CMOS process. The sensor is inseparable from thereadout electronics, since both of them are integrated on the same, low-resistivity silicon wafer. The basic pixel configuration comprises only three MOS transistors and a diode collecting the charge through thermal diffusion. The charge is generated inthe thin undepleted epitaxial layer underneath the readout electronics. This approach provides, at low cost, a high resolution and thin device with the whole area sensitive to radiation. Device simulations using the ISE-TCAD package have been carried out to study the charge collection mechanism. In order to demonstrate the viability of the technique, four prototype chips have been fabricated using different submicrometer CMOS processes. The pixel gain has been calibrated using a 55Fe source and thePoisson sequence method. The prototypes have been exposed to high-energy particle beams at CERN. The tests proved excellent detection performances expressed in a single-track spatial resolution of 1.5 μm and detection efficiency close to 100%, resulting from a SNR ratio of more than 30. Irradiation tests showed immunity of MAPS to a level of a few times 1012 n/cm2 and a few hundred kRad of ionising radiation. The ideas for future work, including on-pixel signal amplification, double sampling operation and current mode pixel design are present as well.Les détecteurs de vertex sont importants pour les expériences de la physique des particules, car la connaissance de la saveur présente dans un événement deviendra une question majeure dans le programme de physique auprès du Futur Collisionneur Linéaire. Un capteur monolithique à pixels actifs (MAPS) basé sur une structure originale a été proposé. Le capteur est inséparable de son électronique de lecture, puisque les deux sont intégrés sur la même tranche de silicum basse résistivité qui constitue le substrat classique pour une technologie CMOS. La configuration de base est composée uniquement de trois transistors et d'une diode qui collecte par diffusion thermique la charge. Celle-ci est générée dans la couche épitaxiale mince, non-désertée en dessous du circuit de lecture. Cela permet d'obtenir un détecteur mince, de haute résolution, d'une surface entièrement sensible à la radiation et d'un faible coût de fabrication. Les simulations détaillées ont été effectuées en utilisant le logiciel ISE-TCAD pour étudier le mécanisme de collection de charge. Quatre prototypes ont été fabriqués en technologies CMOS submicroniques pour démontrer la viabilité de cette technique. Le gain des pixels a été calibré par irradiation à l'aide d'une source 55Fe et en appliquant la méthode fondée sur la séquence de Poisson. Les prototypes ont été également exposés aux faisceaux de particules de haute énergie au CERN. D'excellentes performances de détection ont été prouvées. Elles s'expriment par un rapport signal sur bruit supérieur à 30, une résolution spatiale de 1.5 μm et une efficacité de détection proche de 100%. Les tests d'irradiation ont démontré une résistance aux flux de neutrons jusqu'a quelques 1012 n/cm2 et une résistance aux rayonnements ionisants jusqu'à quelques centaines kRad. Des idées futures telles que l'amplification du signal sur le pixel, le double échantillonnage ainsi que la conception d'un pixel en mode courrant ont été également présentées

Monolithic pixel detectors in a deep submicron SOI process

A compact charge-signal processing chain, composed of a two-stage semi-gaussian preamplifier-signal shaping filter, a discriminator and a binary counter, implemented in a prototype pixel detector using 0.20 {micro}m CMOS Silicon on Insulator process, is presented. The gain of the analog chain was measured 0.76 V/fC at the signal peaking time about 300 ns and the equivalent noise charge referred to the input of 80 e{sup -1}

Monolithic Pixel Detectors in a Deep Submicron SOI Process

Abstract A compact charge-signal processing chain, composed of a two-stage semi-gaussian preamplifier-signal shaping filter, a discriminator and a binary counter, implemented in a prototype pixel detector using 0.20 μm CMOS Silicon on Insulator process, is presented. The gain of the analog chain was measured 0.76 V/fC at the signal peaking time about 300 ns and the equivalent noise charge referred to the input of 80 e -

A new concept of vertically integrated pattern recognition associative memory

Hardware-based pattern recognition for fast triggering on particle tracks has been successfully used in high-energy physics experiments for some time. The CDF Silicon Vertex Trigger (SVT) at the Fermilab Tevatron is an excellent example. The method used there, developed in the 1990's, is based on algorithms that use a massively parallel associative memory architecture to identify patterns efficiently at high speed. However, due to much higher occupancy and event rates at the LHC, and the fact that the LHC detectors have a much larger number of channels in their tracking detectors, there is an enormous challenge in implementing fast pattern recognition for a track trigger, requiring about three orders of magnitude more associative memory patterns than what was used in the original CDF SVT. Scaling of current technologies is unlikely to satisfy the scientific needs of the future, and investments in transformational new technologies need to be made. In this paper, we will discuss a new concept of using the emerging 3D vertical integration technology to significantly advance the state-of-the-art for fast pattern recognition within and outside HEP. A generic R and D proposal based on this new concept, with a few institutions involved, has recently been submitted to DOE with the goal to design and perform the ASIC engineering necessary to realize a prototype device. The progress of this R and D project will be reported in the future. Here we will only focus on the concept of this new approach