29 research outputs found

    Technology for satellite power conversion

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    Components were examined that will be needed for high frequency rectenna devices. The majority of the effort was spent on measuring the directivity and efficiency of the half-wave dipole antenna. It is felt that the antenna and diode should be roughly optimized before they are combined into a rectenna structure. An integrated low pass filter had to be added to the antenna structure in order to facilitate the field pattern measurements. A calculation was also made of the power density of the Earth's radiant energy as seen by satellites in Earth orbit. Finally, the feasibility of using a Metal-Oxide-Metal (MOM) diode for rectification of the received power was assessed

    Technology for satellite power conversion

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    The work is this reporting period was concentrated on electronically calibrating the bolometer detectors. The calibration is necessary for two reasons: first, the power delivered to the rectifying circuit must be known in order to choose a diode with the appropriate barrier height, and second, the power captured by the antenna must be measured if the efficiency of the rectenna is to be divided into antenna efficiency and rectification efficiency. The millimeter wave region operation of the bolometers was simulated with a VHF (10 to 90 MHz) test signal. These detectors are accurate to within roughly 10%. The typical responsivity of the bolometers is 10 volts/watt and the NEP at 20 Hz is 5 times 10 to the minus 9th power W(Hz)-1/2

    Technology for satellite power conversion

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    The work performed in this reporting period has concentrated on the metal-oxide-metal (MOM) diode. The fabrication procedure begins with the deposition of gold probing pads to provide a non-oxidizing contact to test the dc characteristics to the diode accurately. A thin patch capped with an insulating SiO2 layer, is deposited next to form the first half of the diode. The other half of the diode, typically Ni, is deposited completing the conduction path from the oxidized edge of the Ni patch to the opposite gold probing pad. It is important in this step that the last metallization take place without exposing the newly oxidized surface to the atmosphere. Successful production of diodes has been achieved. Work on millimeter wave frequency rectennas incorporating known semiconductor diode technology has been initiated

    Infrared technology for satellite power conversion

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    Successful fabrication of bismuth bolometers led to the observation of antenna action rom array elements. Fabrication of the best antennas arrays was made more facile with finding that increased argon flow during the dc sputtering produced more uniform bismuth films and bonding to antennas must be done with the substrate temperaure below 100 C. Higher temperatures damaged the bolometers. During the testing of the antennas, it was found that the use of a quasi-optical system provided a uniform radiation field. Groups of antennas were bonded in series and in parallel with the parallel configuration showing the greater response

    Technology for satellite power conversion

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    The dipole pattern of the antenna was confirmed and work on the MOM diode began. The antenna - detector structure was modified and the measurement apparatus reconfigured to permit precise antenna pattern measurements. Fabrication of the MOM diode was initiated after antenna action from the new structures was observed. A refined antenna structure was developed. The previous antenna design allowed currents induced by the incident radiation in the bonding wires to flow through the bolometer. The detector was thus responding to both the antenna and bonding wire currents. A low pass filter was added to the antenna structure to improve the detection scheme. The new design uses an interdigitated capacitor to prevent the induced current in the bonding wires from flowing through the detection element

    Advanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits

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    We review the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating Single Flux Quantum(SFQ) digital circuits with very large scale integration on 200-mm wafers: the SFQ4ee and SFQ5ee nodes, where 'ee' denotes the process is tuned for energy efficient SFQ circuits. The former has eight superconducting layers with 0.5 {\mu}m minimum feature size and a 2 {\Omega}/sq Mo layer for circuit resistors. The latter has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm and a thin superconducting MoNx layer (Tc ~ 7.5 K) with high kinetic inductance (about 8 pH/sq) for forming compact inductors. A nonsuperconducting (Tc < 2 K) MoNx layer with lower nitrogen content is used for 6 {\Omega}/sq planar resistors for shunting and biasing of Josephson junctions. Another resistive layer is added to form interlayer, sandwich-type resistors of m{\Omega} range for releasing unwanted flux quanta from superconducting loops of logic cells. Both process nodes use Au/Pt/Ti contact metallization for chip packaging. The technology utilizes one layer of Nb/AlOx-Al/Nb JJs with critical current density, Jc of 100 {\mu}A/{\mu}m^2 and minimum diameter of 700 nm. Circuit patterns are defined by 248-nm photolithography and high density plasma etching. All circuit layers are fully planarized using chemical mechanical planarization (CMP) of SiO2 interlayer dielectric. The following results and topics are presented and discussed: the effect of surface topography under the JJs on the their properties and repeatability, critical current and Jc targeting, effect of hydrogen dissolved in Nb, MoNx properties for the resistor layer and for high kinetic inductance layer, technology of m{\Omega}-range resistors.Comment: 10 pages, 12 figures, 1 table, 27 references. The paper was presented on September 8, 2015 at the 12th European Conference on Applied Superconductivity, EUCAS 2015, 6-10 September 2015, Lyon, France, IEEE Transaction on Applied Superconductivity, 201

    Progress toward superconductor electronics fabrication process with planarized NbN and NbN/Nb layers

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    To increase density of superconductor digital and neuromorphic circuits by 10x and reach integration scale of 10810^8 Josephson junctions (JJs) per chip, we developed a new fabrication process on 200-mm wafers, using self-shunted Nb/Al-AlOx/Nb JJs and kinetic inductors. The process has a layer of JJs, a layer of resistors, and 10 fully planarized superconducting layers: 8 Nb layers and 2 layers of high kinetic inductance materials, Mo2_2N and NbN, with sheet inductance of 8 pH/sq and 3 pH/sq, respectively. NbN films were deposited by two methods: with TcT_c=15.5 K by reactive sputtering of a Nb target in Ar+N2_2 mixture; with TcT_c in the range from 9 K to 13 K by plasma-enhanced chemical vapor deposition (PECVD) using Tris(diethylamido)(tert-butylimido)niobium(V) metalorganic precursor. PECVD of NbN was investigated to obtain conformal deposition and filling narrow trenches and vias with high depth-to-width ratios, which was not possible to achieve using sputtering and other physical vapor deposition (PVD) methods at temperatures below 200oC200 ^oC required to prevent degradation of Nb/Al-AlOx/Nb junctions. Nb layers with 200 nm thickness are used in the process layer stack as ground planes to maintain a high level of interlayer shielding and low intralayer mutual coupling, for passive transmission lines with wave impedances matching impedances of JJs, typically <=50 Ω\Omega, and for low-value inductors. NbN and NbN/Nb bilayer are used for cell inductors. Using NbN/Nb bilayers and individual pattering of both layers to form inductors allowed us to minimize parasitic kinetic inductance associated with interlayer vias and connections to JJs as well as to increase critical currents of the vias. Fabrication details and results of electrical characterization of NbN films, wires, and vias, and comparison with Nb properties are given.Comment: 12 pages, 16 figures, 4 tables, 49 references. Submitted to IEEE TAS on Nov. 10, 202
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