Computation modules and petri nets

Petri-nets are used as a model of processes, and a property of a net called proper termination is defined and discussed. Proper termination is argued to be a useful property which a construct called a "module" should possess. This property assures reentrancy and freedom from deadlock in the net, and a theorem is given concerning the substitution or interchange of modules in a larger environment

Fault-Tolerant, Real-Time, Multi-Core Computer System

A document discusses a fault-tolerant, self-aware, low-power, multi-core computer for space missions with thousands of simple cores, achieving speed through concurrency. The proposed machine decides how to achieve concurrency in real time, rather than depending on programmers. The driving features of the system are simple hardware that is modular in the extreme, with no shared memory, and software with significant runtime reorganizing capability. The document describes a mechanism for moving ongoing computations and data that is based on a functional model of execution. Because there is no shared memory, the processor connects to its neighbors through a high-speed data link. Messages are sent to a neighbor switch, which in turn forwards that message on to its neighbor until reaching the intended destination. Except for the neighbor connections, processors are isolated and independent of each other. The processors on the periphery also connect chip-to-chip, thus building up a large processor net. There is no particular topology to the larger net, as a function at each processor allows it to forward a message in the correct direction. Some chip-to-chip connections are not necessarily nearest neighbors, providing short cuts for some of the longer physical distances. The peripheral processors also provide the connections to sensors, actuators, radios, science instruments, and other devices with which the computer system interacts

Adaptable state based control system

An autonomous controller, comprised of a state knowledge manager, a control executor, hardware proxies and a statistical estimator collaborates with a goal elaborator, with which it shares common models of the behavior of the system and the controller. The elaborator uses the common models to generate from temporally indeterminate sets of goals, executable goals to be executed by the controller. The controller may be updated to operate in a different system or environment than that for which it was originally designed by the replacement of shared statistical models and by the instantiation of a new set of state variable objects derived from a state variable class. The adaptation of the controller does not require substantial modification of the goal elaborator for its application to the new system or environment

Capturing Flight Software Architecture with a Domain-Specific Language

No abstract availabl

Computation modules and petri nets

Petri-nets are used as a model of processes, and a property of a net called proper termination is defined and discussed. Proper termination is argued to be a useful property which a construct called a "module" should possess. This property assures reentrancy and freedom from deadlock in the net, and a theorem is given concerning the substitution or interchange of modules in a larger environment

The Design of a Fault-Tolerant, Real-Time, Multi-Core Computer System

No abstract availabl

The Mars Science Laboratory Entry, Descent, and Landing Flight Software

No abstract availabl

A new interpreter for data flow schemas and its implications for computer architecture

The execution of a program may be viewed as the processing of a statement in a programming language by an underlying interpreter. This report discusses briefly the advantages of a data flow language over conventional programming methods, and then presents a new interpreter for a data flow language. Using as a base the data flow language of Dennis ["First Version of a Data Flow Procedure Language" Computation Structures Group Memo 93, Project MAC, MIT, Nov. 1973], the new interpreter magnifies the apparent asynchrony and speed of data flow, and it does so by (quite literally) exchanging blocks of processors for slices of time. The report gives details of the operation of this new interpreter, and identifies the consequences of the new interpreter on machine architecture and design