System efficient ESD design concept for soft failures

This research covers the topic of developing a systematic methodology of studying electrostatic discharge (ESD)-induced soft failures. ESD-induced soft failures (SF) are non-destructive disruptions of the functionality of an electronic system. The soft failure robustness of a USB3 Gen 1 interface is investigated, modeled, and improved. The injection is performed directly using transmission line pulser (TLP) with varying: pulse width, amplitude, polarity. Characterization provides data for failure thresholds and a SPICE circuit model that describes the transient voltage and current at the victim. Using the injected current, the likelihood of a SF is predicted. ESD protection by transient voltage suppressor (TVS) diodes is numerically simulated in several configurations. The results strongly suggest the viability of using well-established hard failure mitigation techniques for improving SF robustness, and the possibility of using numerical simulation for optimization purposes. A concept of soft failure system efficient ESD design (SF-SEED) is proposed and shown to be effective --Abstract, page iv

Comparing the genetic typing methods for effective surveillance and rabies control in Georgia

A full nucleoprotein gene sequencing of 68 isolates collected from passive rabies surveillance system in Georgia between 2015 and 2016 identified two distinct dog rabies phylogroups, GEO_V1 and GEO_V2, which both belonged to the cosmopolitan dog clade. GEO_V1 was found throughout the country and was further divided into four sub-phylogroups that overlapped geographically; GEO_V2 was found in the southeast region and was closely related to dog rabies in Azerbaijan. A sequence analysis of the full N gene, partial nucleoprotein gene of N-terminal and C-terminal, and the amplicon sequences of pan-lyssavirus RT-qPCR LN34 showed that all four sequencing approaches provided clear genetic typing results of canine rabies and could further differentiate GEO_V1 and GEO_V2. The phylogenetic analysis results vary and were affected by the length of the sequences used. Amplicon sequencing of the LN34 assay positive samples provided a rapid and cost-effective method for rabies genetic typing, which is important for improving rabies surveillance and canine rabies eradication globally

Implementation and Practical Experience with an Automatic Secondary ESD Detection Algorithm

Secondary ESD from a non-grounded decorative metal structure on an electronic device often leads to very large discharge currents and a fast rise time of less than 400 picoseconds. Due to the proximity of this secondary ESD event to the electronics, it is likely to cause soft failures or latch-up. Secondary ESD can be detected in IEC 61000-4-2 setups by monitoring the currents, charge transfer, and sudden current increases due to the secondary ESD. An algorithm has been implemented in a test setup which automatically detects secondary ESD. However, due to pre-pulses, reignition of sparking within the relay, and other effects, the algorithm may lead to false positives and missed secondary ESD. This paper describes the implementation of the algorithm and presents the results of DUT testing

IC Pin Modeling and Mitigation of ESD-Induced Soft Failures

In this article, electrostatic discharge (ESD) induced soft failures (SFs) of a USB3 Gen1 device are investigated by direct transmission line pulse injection with varying pulsewidth, amplitude, and polarity to characterize the failure behavior of the interface and to create a SPICE model of the voltage and current waveform dependent failure thresholds. ESD protection by transient-voltage-suppression diodes is numerically simulated in several configurations. The results show viability of using well-established hard failure mitigation techniques for improving SF robustness. A good agreement between numerical simulation for optimized board design and measurements are achieved. A novel concept of SF system efficient ESD design is proposed and demonstrated to be effective for making decisions during early product development, in board designing and prototyping phase

Sensitivity of NRZ and PAM4 Signaling Schemes to Channel Insertion Loss Deviation

Paper discusses channel Insertion Loss Deviation (ILD) effects on binary and multi-level signaling in high-speed link design. Overview of ILD phenomenon is given and its sources in a multi-stage transmission line are discussed. Comparison tests are provided for channels with different amount of ILD. The test channels were simulated to mimic backplane channels with daughter cards. In order to cause significant ILD, impedance mismatches and interconnect parasitic effects were introduced into the model. Results are analyzed in terms of eye diagram degradations due to ILD induced ISI noise

Software-Assisted Detection Methods for Secondary ESD Discharge During IEC 61000-4-2 Testing

When an electrostatic discharge (ESD) event reaches a nongrounded metallic part within a product, the voltage of this metal with respect to ground will increase. If the isolation to the ground is insufficient, a secondary ESD event can occur. As secondary ESD often leads to system upset or damage, and to poorly reproducible results, it is important to detect the occurrence of secondary ESD. If the discharge current is monitored using an oscilloscope, the test equipment may miss the secondary discharge waveform. This is because the time delay between the primary and secondary discharge events can vary between nanoseconds to milliseconds. Present oscilloscopes do not offer functionality to autodetect a secondary discharge event. The goal of this study is to analyze different types of secondary discharge events acquired with various measurement setups and identify waveform parameters for software-assisted detection methods. A learning sequence is proposed for identifying secondary ESD events starting from low ESD gun test voltages. The data are analyzed with respect to the waveform parameters such as the vertical threshold of the rising edge, the dI/dt of the current waveform, and total charge delivered, which enable automatic detection of secondary ESD while monitoring the discharge waveform at the ESD gun tip

Optimizing Measurement SNR for Weak Near-Field Scanning Applications

Conventional near-field scanning techniques often employ a general setup such as: broadband near-field probe output connected to a chain of amplifiers through a coaxial cable to a spectrum analyzer. In this paper, we investigated how the signal to noise ratio is influenced by the coaxial connection between the probe output and the first amplifier, types of probes, cooling the probes with liquid nitrogen and the amplifier\u27s noise figure. Eliminating cabling between probe and first amplifier, and using a low noise amplifiers helped increase signal-to-noise ratio by ~10dB. Further, liquid nitrogen is used to cool down a tunable resonant probe. This increases quality factor of the resonance and improves sensitivity. Thus, SNR is further improved by 10-12dB compared to a similar broadband setup

Pin Specific ESD Soft Failure Characterization using a Fully Automated Set-Up

A fully automated system is developed for the systematic characterization of soft failure robustness for a DUT. The methodology is founded on software-based detection methods and applied to a USB3 interface. The approach is extendable to other interfaces and measurement-based failure detection methods

TVS Transient Behavior Characterization and Spice based Behavior Model

A SPICE model for the transient behavior of TVS devices is presented. TVS devices under ESD stress do not turn on instantaneously and a transient overshoot can be observed at start-up. This model includes small signal RF behavior, quasi-static VI curve, inductive overshoot, conductivity modulation, snapback trigger delay and the ability to be used on any SPICE simulation

An Application of System Level Efficient ESD Design for High- Speed USB3.x Interface

A high-speed USB3.x IO is analyzed using the System level efficient ESD design methodology [1] using on-board current and voltage measurements for the TX and RX pins. The interactions between external ESD protection device and the on-chip ESD protection circuit is investigated in measurement and simulation