Impact of the W scaling on bias temperature instability in nanowire transistors

International audienc

Temperature and field dependence of stress induced leakage currents in very thin (<5 nm) gate oxides

International audienceWe have studied the electric field and temperature dependence of stress induced leakage currents that appear in 3.8 and 4.7 nm thick SiO2 oxides of metal oxide semiconductor structures after Fowler–Nordheim (FN) electron injections from the poly-Si gate and localized hot-hole injections from the p-Si substrate. Constant voltage or constant current stressing modes were used, which did not produce any difference in stress induced leakage currents (SILC) increase. A Schottky law apparently fits the field dependence of such currents in 4.7 nm samples, but the slope found in 3.8 nm thick oxides disagrees with the theoretical prediction. Moreover, the field dependence of the thermal activation energy found is much less than the Schottky prediction, which rules out the possibility of a thermoionic process to fully explain such currents in our samples. We show that a direct tunneling law, modified to account for a mechanism assisted by stress induced baricentric neutral defects, does correctly fit the oxide field dependence of these currents and is consistent with the observed thermal activation energy

Effective work function modulation by sacrificial aluminium on HfON-based 14nm devices

International audienc

Impact of bulk defects in hydrogenated amorphous Si layers on performance of high efficiency HeteroJunctions solar cells assessed by 2D modeling

International audienc

Doping Solutions for Advanced CMOS high-k / metal Gate Engineering

International audienc

Electrical Conduction in 10nm Thin Polysilicon Wires from 4 to 400K and Their Operation for Hybrid Memory

This paper reports on the experimental investigation of conduction mechanisms in gated ultra-thin polysilicon nanowires (polySiNW) over a wide range of temperature: from 4 to 400 K. Some irregular Coulomb oscillations (CO) are observed at temperatures lower than 200K showing several periods due to the random mixture of grain sizes (5 – 20 nm). We report increased oscillations at intermediate range of temperatures (between 50 and 150 K) and at high drain voltages in polySiNW with a mixture of grain sizes. Monte Carlo (MC) simulations performed on an array of conductive islands connected to each other by tunnel junctions (modeling the nanograin polysilicon) validate the experimental observations and a first order theory is proposed. Finally, the V-shape (ambipolar) drain current versus gate voltage $(I_{DS}-V_{GS})$ characteristic and related hysteresis of the polySiNW is exploited for building a novel hybrid polySiNW-NMOS memory circuit cell

Modeling the Dynamic Variability Induced by Charged Traps in a Bilayer Gate Oxide

International audienceIn this paper, we revisit the classic single layer defect centric model (DCM), largely used in reliability studies, in the more realistic case of bilayer gate oxide transistors integrating an interface layer and a high-K dielectric. The Monte Carlo method and 3-D electrostatic simulations are used to determine the impact of the traps present in both layers on the Vt of transistors. It is proved that the DCM is able to capture the trap-induced variability of bilayer transistors but with effective model parameters, which have no more a true physical meaning as in the case of the single layer gate oxide. An extended DCM, accounting for a two trap distributions, is then proposed to better explain the degradation measured on bilayer transistors. Finally, this extended DCM finds another application in the evaluation of the bias temperature instability-induced variability of static RAM cells

Piezoresistivity in unstrained and strained SOI MOSFETs

session: FDSOIInternational audienceWe hereby present the extraction and the study of piezoresistive (PR) coefficients in MOSFETs built on unstrained and strained SOI substrates. We have evidenced a strong dependence of these PR with the inversion charge density in particular for PMOS. These results are well explained by the Si bandstructure calculation which enlightens the effect of the strain and of the electric confinement on carrier mobility, up to high tensile strain values

Novel C-V measurements based method for the extraction of GaN buffer layer residual doping level in HEMT

session 9: Novel device architecture characterizationInternational audienceThis paper presents a new methodology to characterize the GaN buffer doping level which is a critical parameter for epitaxial fabrication of GaN wafers. As demonstrated in this study, its characterization is challenging due to parasitic effects. Capacitance-Voltage (C-V) measurements are carried out on a Metal Insulator Semiconductor (MIS) structure with a gate on Al 2 O 3 dielectric using a novel configuration. The experimental study is validated with a self-consistent Poisson-Schrodinger (PS) simulation. Finally, our methodology is applied to a new generation of GaN buffer through a fully and partially (without any contacts) processed wafer, with a Hg-probe C-V measurement performed on the partially processed one

Effects of negative bias stress on trapping properties of AlGaN/GaN Schottky barrier diodes

International audienc