Energy Optimization in NCFET-based Processors

Energy consumption is a key optimization goal for all modern processors. Negative Capacitance Field-Effect Transistors (NCFETs) are a leading emerging technology that promises outstanding performance in addition to better energy efficiency. Thickness of the additional ferroelectric layer, frequency, and voltage are the key parameters in NCFET technology that impact the power and frequency of processors. However, their joint impact on energy optimization has not been investigated yet.In this work, we are the first to demonstrate that conventional (i.e., NCFET-unaware) dynamic voltage/frequency scaling (DVFS) techniques to minimize energy are sub-optimal when applied to NCFET-based processors. We further demonstrate that state-of-the-art NCFET-aware voltage scaling for power minimization is also sub-optimal when it comes to energy. This work provides the first NCFET-aware DVFS technique that optimizes the processor\u27s energy through optimal runtime frequency/voltage selection. In NCFETs, energy-optimal frequency and voltage are dependent on the workload and technology parameters. Our NCFET-aware DVFS technique considers these effects to perform optimal voltage/frequency selection at runtime depending on workload characteristics. Results show up to 90 % energy savings compared to conventional DVFS techniques. Compared to state-of-the-art NCFET-aware power management, our technique provides up to 72 % energy savings along with 3.7x higher performance

Memory Latency Distribution-Driven Regulation for Temporal Isolation in MPSoCs

Temporal isolation is one of the most significant challenges that must be addressed before Multi-Processor Systems-on-Chip (MPSoCs) can be widely adopted in mixed-criticality systems with both time-sensitive real-time (RT) applications and performance-oriented non-real-time (NRT) applications. Specifically, the main memory subsystem is one of the most prevalent causes of interference, performance degradation and loss of isolation. Existing memory bandwidth regulation mechanisms use static, dynamic, or predictive DRAM bandwidth management techniques to restore the execution time of an application under contention as close as possible to the execution time in isolation. In this paper, we propose a novel distribution-driven regulation whose goal is to achieve a timeliness objective formulated as a constraint on the probability of meeting a certain target execution time for the RT applications. Using existing interconnect-level Performance Monitoring Units (PMU), we can observe the Cumulative Distribution Function (CDF) of the per-request memory latency. Regulation is then triggered to enforce first-order stochastical dominance with respect to a desired reference. Consequently, it is possible to enforce that the overall observed execution time random variable is dominated by the reference execution time. The mechanism requires no prior information of the contending application and treats the DRAM subsystem as a black box. We provide a full-stack implementation of our mechanism on a Commercial Off-The-Shelf (COTS) platform (Xilinx Ultrascale+ MPSoC), evaluate it using real and synthetic benchmarks, experimentally validate that the timeliness objectives are met for the RT applications, and demonstrate that it is able to provide 2.2x more overall throughput for NRT applications compared to DRAM bandwidth management-based regulation approaches

Surveillance of acute SARS-CoV-2 infections in elementary schools and daycare facilities in Bavaria, Germany (09/2020–03/2021)

Introduction: Here we report our results of a multi-center, open cohort study ("COVID-Kids-Bavaria") investigating the distribution of acute SARS-CoV-2 infections among children and staff in 99 daycare facilities and 48 elementary schools in Bavaria, Germany. Materials and Methods: Overall, 2,568 children (1,337 school children, 1,231 preschool children) and 1,288 adults (466 teachers, 822 daycare staff) consented to participate in the study and were randomly tested in three consecutive phases (September/October 2020, November/December 2020, March 2021). In total, 7,062 throat swabs were analyzed for SARS-CoV-2 by commercial RT-PCR kits. Results: In phase I, only one daycare worker tested positive. In phase II, SARS-CoV-2 was detected in three daycare workers, two preschool children, and seven school children. In phase III, no sample tested positive. This corresponds to a positive test rate of 0.05% in phase I, 0.4% in phase II and 0% in phase III. Correlation of a positive PCR test result with the local-7-day incidence values showed a strong association of a 7-day-incidence of more than 100/100,000 as compared to <100/100,000 (OR = 10.3 [1.5-438], p < 0.005). After phase III, antibody testing was offered to 713 study participants in elementary schools. A seroprevalence rate of 7.7% (students) and 4.5% (teachers) was determined. Discussion: During the initial waves of the SARS-CoV-2 pandemic, the risk of a positive SARS-CoV-2 result correlated positively with the local 7-day incidence. Hence, the occurrence of SARS-CoV-2 infections were reflected in schools and daycare facilities. An increased risk of SARS-CoV-2 transmission in the setting of daycare and elementary schooling was unlikely