EFFICIENT IMPLEMENTATION OF TELECOMMUNICATION ATM PROTOCOL STACK FOR TERMINAL SYSTEMS

Η ΔΙΔΑΚΤΟΡΙΚΗ ΔΙΑΤΡΙΒΗ ΠΕΡΙΛΑΜΒΑΝΕΙ ΕΡΕΥΝΑ ΓΙΑ ΤΗ ΣΧΕΔΙΑΣΗ ΑΠΟΔΟΤΙΚΩΝ ΤΕΡΜΑΤΙΚΩΝ ΣΥΣΤΗΜΑΤΩΝ ΕΥΡΕΙΑΣ ΖΩΝΗΣ ΚΑΛΥΠΤΟΝΤΑΣ ΘΕΜΑΤΑ ΥΛΙΚΟΥ ΚΑΙ ΛΟΓΙΣΜΙΚΟΥ. ΠΑΡΟΥΣΙΑΖΟΝΤΑΙ ΜΕΤΡΗΣΕΙΣ ΑΠΟΔΟΣΗΣ ΠΟΥ ΕΧΟΥΝ ΠΑΡΘΕΙ ΧΡΗΣΙΜΟΠΟΙΩΝΤΑΣ ΕΝΑ ΠΕΙΡΑΜΑΤΙΚΟ ΑΤΜ ΤΕΡΜΑΤΙΚΟ ΠΟΥ ΑΝΑΠΤΥΧΘΗΚΕ ΣΤΟ ΕΡΓΑΣΤΗΡΙΟ ΤΗΛΕΠΙΚΟΙΝΩΝΙΩΝ ΤΟΥ ΕΜΠ. Η ΔΙΑΤΡΙΒΗ ΕΡΕΥΝΑ ΤΟ ΘΕΜΑ ΑΝΑΠΤΥΞΗΣ ΟΛΟΚΛΗΡΗΣ ΤΗΣ ΣΤΟΙΒΑΣ ΠΡΩΤΟΚΟΛΛΩΝ ΣΥΝΔΥΑΖΟΝΤΑΣ ΠΟΛΛΕΣ ΠΡΟΓΡΑΜΜΑΤΙΣΤΙΚΕΣ ΤΕΧΝΙΚΕΣ ΚΑΙ ΠΡΟΣΑΡΜΟΖΟΝΤΑΣ ΤΗΝ ΧΡΗΣΗ ΤΟΥΣ ΣΤΙΣ ΑΠΑΙΤΗΣΕΙΣ ΤΗΣ ΑΡΧΙΤΕΚΤΟΝΙΚΗΣ ΕΠΙΠΕΔΩΝ ΟΠΩΣ ΕΦΑΡΜΟΖΕΤΑΙ ΣΤΙΣ ΕΠΙΚΟΙΝΩΝΙΕΣ ΕΥΡΕΙΑΣ ΖΩΝΗΣ. ΕΠΙΠΛΕΟΝ, ΑΝΑΠΤΥΣΣΕΤΑΙ ΕΝΑ ΣΧΗΜΑ ΔΙΑΧΕΙΡΙΣΗΣ ΓΙΑ ΣΤΟΙΒΑ ΠΡΩΤΟΚΟΛΛΩΝ ΚΑΙΠΑΡΟΥΣΙΑΖΕΤΑΙ Ο ΑΠΑΙΤΟΥΜΕΝΟΣ ΕΛΕΓΚΤΗΣ ΠΟΥ ΚΑΛΕΙΤΑΙ ΕΛΕΓΚΤΗΣ ΡΟΗΣ ΔΕΔΟΜΕΝΩΝ. ΕΠΙΣΗΣ, ΠΑΡΟΥΣΙΑΖΕΤΑΙ ΕΝΑΣ ΕΠΕΞΕΡΓΑΣΤΗΣ ΣΤΟΙΒΑΣ ΜΕ ΚΑΛΑ ΟΡΙΣΜΕΝΟΥΣ ΣΤΟΧΟΥΣ: ΕΛΑΧΙΣΤΗ ΜΕΤΑΦΟΡΑ ΔΕΔΟΜΕΝΩΝ ΜΕΤΑΞΥ ΤΩΝ ΕΠΙΠΕΔΩΝ, ΤΟΠΟΘΕΤΗΣΗ ΤΟΥ ΩΦΕΛΙΜΟΥ ΦΟΡΤΙΟΥΤΗΣ ΣΤΟΙΒΑΣ ΣΕ ΣΥΝΕΧΟΜΕΝΗ ΜΝΗΜΗ ΚΑΙ ΑΠΟΔΟΤΙΚΗ ΕΚΤΕΛΕΣΗ ΒΑΣΙΣΜΕΝΗ ΣΕ ΣΩΛΗΝΟΕΙΔΗ ΑΡΧΙΤΕΚΤΟΝΙΚΗ ΠΡΟΣΑΡΜΟΣΜΕΝΗ ΣΤΑ ΔΙΚΤΥΑ ΕΥΡΕΙΑΣ ΖΩΝΗΣ. ΠΑΡΟΥΣΙΑΖΕΤΑΙ ΜΙΑ ΔΥΑΔΙΚΗ ΣΧΕΣΗ ΜΕΤΑΞΥ ΤΟΥ ΠΟΜΠΟΥ ΚΑΙ ΤΟΥ ΔΕΚΤΗ. Η ΛΥΣΗ ΠΟΥ ΠΡΟΤΕΙΝΕΤΑΙ, ΕΜΦΑΝΙΖΕΙ ΠΟΛΥ ΓΡΗΓΟΡΗ ΕΠΕΞΕΡΓΑΣΙΑ ΣΕ ΠΕΡΙΒΑΛΛΟΝ ΧΩΡΙΣ ΛΑΘΗ ΜΕ ΜΙΚΡΟ ΚΟΣΤΟΣ ΓΙΑ ΤΟΝ ΧΕΙΡΙΣΜΟ ΠΡΟΒΛΗΜΑΤΩΝ ΤΟΥ ΔΙΚΤΥΟΥ. ΧΑΡΑΚΤΗΡΙΣΤΙΚΕΣ ΠΕΡΙΠΤΩΣΕΙΣ ΕΦΑΡΜΟΓΗΣ, ΣΥΓΚΡΙΤΙΚΑΑΠΟΤΕΛΕΣΜΑΤΑ ΚΑΙ ΜΕΤΡΗΣΕΙΣ ΑΠΟΔΟΣΗΣ ΚΑΘΙΕΡΩΝΟΥΝ ΤΑ ΠΛΕΟΝΕΚΤΗΜΑΤΑ ΤΗΣ ΠΡΟΣΕΓΓΙΣΗΣ ΜΑΣ ΣΕ ΣΧΕΣΗ ΜΕ ΑΥΤΕΣ ΠΟΥ ΠΡΟΤΕΙΝΟΝΤΑΙ ΣΤΗ ΒΙΒΛΙΟΓΡΑΦΙΑ. ΤΕΛΟΣ, (ΠΕΡΙΚΟΠΗΠΕΡΙΛΗΨΗΣ)THIS DOCTORAL THESIS INCLUDES RESEARCH FOR THE DESIGN OF EFFICIENT BROADBAND TERMINAL SYSTEMS COVERING BOTH HARDWARE AND SOFTWARE ISSUES. PERFORMANCE MEASUREMENTS ARE PRESENTED THAT HAVE BEEN TAKEN USING AN EXPERIMENTAL ATM PC ADAPTER, DEVELOPED WITHIN THE TELECOMS LAB OF NTUA. THE THESIS ADDRESSES THE ISSUE OFEFFICIENTLY IMPLEMENTING ENTIRE COMMUNICATION PROTOCOL STACKS BY INVOLVING SEVERAL PROGRAMMING TECHNIQUES AND TAILORING THEIR USE FOR THE REQUISITES OF A LAYERED ARCHITECTURE AS APPLIED IN BROADBAND COMMUNICATIONS. FURTHERMORE, IT DEVELOPS A MANAGEMENT SCHEME FOR LAYERED PROTOCOLS STACKS WHILE IT PRESENTS THE REQUIRED CONTROLLER CALLED DATA FLOW CONTROLLER. MOREVER, A STACK PROCESSOR IS PRESENTED WITH WELL SPECIFIED GOALS: MINIMAL INTERLAYER MOVEMENT OF DATA, STACK PAYLOAD PLACED IN CONTIGUOUS MEMORY, PERFORMANT EXECUTION BASED ON PIPELINING AND ADAPTED FOR BROADBAND NETWORKS. A RECEIVER - TRANSMITTER DUALITY PRINCIPLE IS FORMULATED. THE GIVEN SOLUTION ACCOMPLISHES EXTREMELY FAST PROCESSING IN AN ERROR FREE ENVIRONMENT AT THE COST OF SOME PROCEDURAL OVERHEAD FOR HANDLING NETWORK IMPAIREMENTS. CHARACTERISTIC APPLICATION CASES, COMPARATIVE RESULTS AND PERFORMANCE MEASUREMENTS ESTABLISH THE ADVANTAGES OF OUR APPROACH OVERTHOSE SUGGESTED AND IMPLEMETNED ELSEWHERE. FINALLY, A REAL TIME ARRAY - BASEDMEMORY MANAGING MODULE IS PRESENTED. (ABSTRACT TRUNCATED

Neural Network-Based Solar Irradiance Forecast for Edge Computing Devices

Aiming at effectively improving photovoltaic (PV) park operation and the stability of the electricity grid, the current paper addresses the design and development of a novel system achieving the short-term irradiance forecasting for the PV park area, which is the key factor for controlling the variations in the PV power production. First, it introduces the Xception long short-term memory (XceptionLSTM) cell tailored for recurrent neural networks (RNN). Second, it presents the novel irradiance forecasting model that consists of a sequence-to-sequence image regression NNs in the form of a spatio-temporal encoder–decoder including Xception layers in the spatial encoder, the novel XceptionLSTM in the temporal encoder and decoder and a multilayer perceptron in the spatial decoder. The proposed model achieves a forecast skill of 16.57% for a horizon of 5 min when compared to the persistence model. Moreover, the proposed model is designed for execution on edge computing devices and the real-time application of the inference on the Raspberry Pi 4 Model B 8 GB and the Raspberry Pi Zero 2W validates the results

PRO3: A hydrid NPU architectures

Summarization: As the telecommunications industry recovers from the severe downturn of recent years, data traffic continues to exhibit a rate of increase that outpaces advances in VLSI technology. Therefore, lowering overall system cost at network processing nodes and maximizing network utilization - hence revenues - remain extremely important objectives. To address these issues, new semiconductor devices called network processing units (NPUs) have emerged. They are optimized to provide programmable processing of protocol data units (PDUs) in networks with diverse requirements while efficiently supporting current and emerging protocols and services. NPUs promise to deliver an ASICs speed with a CPU's programmability, thus augmenting the capacity and features of network nodes that forward and manipulate data traffic. The Programmable Protocol Processor (PRO3) system reduces the overhead incurred by common "BRUTE-FORCE" architectures by using the least-required hardware resources for certain common well-defined tasks.Presented on: IEEE Micr