On Co-Optimization Of Constrained Satisfiability Problems For Hardware Software Applications

Manufacturing technology has permitted an exponential growth in transistor count and density. However, making efficient use of the available transistors in the design has become exceedingly difficult. Standard design flow involves synthesis, verification, placement and routing followed by final tape out of the design. Due to the presence of various undesirable effects like capacitive crosstalk, supply noise, high temperatures, etc., verification/validation of the design has become a challenging problem. Therefore, having a good design convergence may not be possible within the target time, due to a need for a large number of design iterations. Capacitive crosstalk is one of the major causes of design convergence problems in deep sub-micron era. With scaling, the number of crosstalk violations has been increasing because of reduced inter-wire distances. Consequently only the most severe crosstalk faults are fixed pre-silicon while the rest are tested post-silicon. Testing for capacitive crosstalk involves generation of input patterns which can be applied post-silicon to the integrated circuit and comparison of the output response. These patterns are generated at the gate/ Register Transfer Level (RTL) of abstraction using Automatic Test Pattern Generation (ATPG) tools. In this dissertation, anInteger Linear Programming (ILP) based ATPG technique for maximizing crosstalk induced delay increase at the victim net, for multiple aggressor crosstalk faults, is presented. Moreover, various solutions for pattern generation considering both zero as well as unit delay models is also proposed. With voltage scaling, power supply switching noise has become one of the leading causes of signal integrity related failures in deep sub-micron designs. Hence, during power supply network design and analysis of power supply switching noise, computation of peak supply current is an essential step. Traditional peak current estimation approaches involve addition of peak current associated with all the CMOS gates which are switching in a combinational circuit. Consequently, this approach does not take the Boolean and temporal relationships of the circuit into account. This work presents an ILP based technique for generation of an input pattern pair which maximizes switching supply currents for a combinational circuit in the presence of integer gate delays. The input pattern pair generated using the above approach can be applied post-silicon for power droop testing. With high level of integration, Multi-Processor Systems on Chip (MPSoC) feature multiple processor cores and accelerators on the same die, so as to exploit the instruction level parallelism in the application. For hardware-software co-design, application programming model is based on a Task Graph, which represents task dependencies and execution/transfer times for various threads and processes within an application. Mapping an application to an MPSoC traditionally involves representing it in the form of a task graph and employing static scheduling in order to minimize the schedule length. Dynamic system behavior is not taken into consideration during static scheduling, while dynamic scheduling requires the knowledge of task graph at runtime. A run-time task graph extraction heuristic to facilitate dynamic scheduling is also presented here. A novel game theory based approach uses this extracted task graph to perform run-time scheduling in order to minimize total schedule length. With increase in transistor density, power density has gone up substantially. This has lead to generation of regions with very high temperature called Hotspots. Hotspots lead to reliability and performance issues and affect design convergence. In current generation Integrated Circuits (ICs) temperature is controlled by reducing power dissipation using Dynamic Thermal Management (DTM) techniques like frequency and/or voltage scaling. These techniques are reactive in nature and have detrimental effects on performance. Here, a look-ahead based task migration technique is proposed, in order to utilize the multitude of cores available in an MPSoC to eliminate thermal emergencies. Our technique is based on temperature prediction, leveraging upon a novel wavelet based thermal modeling approach. Hence, this work addresses several optimization problems that can be reduced to constrained max-satisfiability, involving integer as well as Boolean constraints in hardware and software domains. Moreover, it provides domain specific heuristic solutions for each of them

The Control Stage of a Modular Multilevel Converter-based Arbitrary Wave shape Generator for Dielectric Testing of High Voltage Grid Assets

A Modular Multilevel Converter (MMC)-based Arbitrary Wave shape Generator (AWG) for High Voltage (HV) testing faces challenges in the control hardware to generate kHz-range high-frequency waveforms. Real Time Simulators (RTS) provide a simple way to implement the control of the MMC-based AWG in the FPGA. One of the commercially available RTS named Typhoon HIL is found to satisfy the small simulation step requirement such as minimum of 200 ns for generating kHz-range high-frequency waveforms. The performance of Typhoon HIL device is demonstrated with a scaled-down prototype of MMC-based AWG where sinusoidal and other arbitrary waveforms are generated up to 5kHz with a THD less than 5 %

Implementation of Active Damping Control Methodology on Modular Multilevel Converter(MMC)-Based Arbitrary Wave Shape Generator Used for High Voltage Testing

In order to damp the resonance in the MMC-based Arbitrary Wave shape Generator (AWG) used for high voltage testing, an active damping control methodology is proposed in this paper instead of the passive damping with an arm resistor. It is vital to ensure the system’s stability when such an active damping closed loop control is implemented. Consequently, optimal parameters of a PI controller are designed by analyzing the stability margins of the involved transfer function using Bode-Plots. The performance of the designed active damping control methodology and the PI controller have been demonstrated with a 50 Hz sinusoidal waveform and arbitrary waveforms such as triangular, trapezoidal, and complex waveforms in MATLAB-Simulink. These results proves that the output voltage can track the reference without any reasonable error and does not contain any resonant frequency. Additionally, the Total Harmonic Distortion (THD) of the sinusoidal waveform and other arbitrary waveforms is less than 1% with the Phase Shift Carrier (PSC) modulation technique

2-(Benzene­sulfonamido)pyridinium perchlorate

In the title compound, C11H11N2O2S+·ClO4 −, the dihedral angle between the benzene and pyridinium rings is 87.33 (10)°. An intra­molecular N—H⋯O inter­action, with an S=O-bonded O atom as receptor, occurs in the cation. In the crystal structure, ion pairs occur, being linked by strong N—H⋯O hydrogen bonds. The perchlorate anion plays a further role in the mol­ecular packing by accepting several weak C—H⋯O inter­actions

Design of Integrated Hybrid Configuration of Modular Multilevel Converter and Marx Generator to Generate Complex Waveforms for Dielectric Testing of Grid Assets

This article proposes a new configuration of a modular multilevel converter (MMC) and a Marx generator to generate fast-rising impulse waveforms. This new configuration improves the capabilities of the MMC-based high voltage arbitrary wave shape generator to generate fast-rising impulse since the MMC topology faces many inherent limitations. Similar to the conventional superimposed circuit of the ac transformer or dc rectifier circuit with the Marx generator, three hybrid circuits of MMC and the Marx generator are introduced, where the most optimal choice is made considering the practical aspects of testing, such as the size, cost, and preparation time. Then, a detailed analytical study is performed on the Marx generator circuit and the MMC circuit, and both circuits are coupled together to deliver a complete guideline on choosing various system parameters when the impulse wave shape and the load capacitor are given. The concept of this new hybrid configuration is demonstrated with a scaled-down prototype where the impulse with a rise time of 1 μs is superimposed on different arbitrary wave shapes. Similarly, the MATLAB-Simulink simulation model validates the proposed configuration for a 200, k V dc link voltage and 67 submodules with the desired impulse performance.</p

Using metrics and sustainability considerations to evaluate the use of bio-based and non-renewable Brønsted acidic ionic liquids to catalyse Fischer esterification reactions

Background Ionic liquids have found uses in many applications, one of which is the joint solvation and catalysis of chemical transformations. Suitable Brønsted acidic ionic liquids can be formed by combining lactams with sulphonic acids. This work weighs up the relative benefits and disadvantages of applying these Brønsted acidic ionic liquid catalysts in esterifications through a series of comparisons using green chemistry metrics. Results A new bio-based ionic liquid was synthesised from N-methyl pyrrolidinone and p-cymenesulphonic acid, and tested as a catalyst in three Fischer esterifications under different conditions. An evaluation of the performance of this Brønsted acidic ionic liquid was made through the comparison to other ionic liquid catalysts as well as conventional homogeneous Brønsted acids. Conclusion Extending the argument to feedstock security as well as mass utilisation, ultimately in most instances traditional mineral acids appear to be the most sensible option for Brønsted acid esterification catalysts. Ester yields obtained from Brønsted acidic ionic liquid catalysed procedures were modest. This calls into question the diversity of research exploring esterification catalysis and the role of ionic liquids in esterifications