Characterization and Lambert – W Function based modeling of FDSOI five-gate qubit MOS devices down to cryogenic temperatures

International audienceFD-SOI five-gate (5G) qubit MOS devices are electrically characterized in linear regime down to deep cryogenic temperatures. The Lambert-W function is successfully used for the modelling of such 5G MOS devices from subthreshold regime to strong inversion. Its applicability is demonstrated down to 20 K. The 5G device is modeled as a series of five independent transistors: the “active” one, that directly controls the current, and the “external” ones, that act as access resistances. The Lambert-W function enables toaccurately determine the inversion charge and the active channel resistance from weak to strong inversion. This approach allows reconstructing the drain current characteristicavoiding the evaluation of the mobility attenuation factors. The main device parameters are extracted versus temperature. Finally, the role of different scattering mechanisms has been investigated, underlying the impact of neutral defects for the gates in proximity of source and drain

Buried PN junctions impact on the performances of an inductor at RF frequencies in the presence of parasitic surface conduction

International audienceThis paper shows the effect of buried PN junctions on the performances of inductors, and investigates the limitation of the subsequent substrate losses. We provide a simple and robust model that enables a precise evaluation of the substrate losses for devices fabricated on various substrates, and using various PN junctions implantation conditions. We point out that buried PN junctions are very efficient to counter the parasitic surface conduction, increasing the quality factor of inductors by more than 30% in the best experimental conditions. However, this integration does not reach the same performance level as trap rich substrates measured in the same conditions

Experimental Analysis and Modeling of Self-Heating and Thermal Coupling in 28 nm FD-SOI CMOS Transistors Down to Cryogenic Temperatures

International audienceThermal effects are a major concern for efficient cryoCMOS circuit design. This work presents an experimental analysis of self-heating effect and thermal propagation in FD-SOI technology, measured from room temperature (300K) down to 4.2K, using the gate resistance thermometry technique. The channel temperature increase and the in-plane temperature profile were investigated and analytically modeled, together with thermal coupling between simultaneously operating devices. We demonstrated a major constraint for extremely low temperature operation due to abrupt channel temperature rise even at sub-1mW input power, which propagates over hundreds of nanometers along the Si layer. Thermal coupling was identified as a source for self-heating aggravation, and needs to be particularly optimized to limit the heating of cryo-circuits

Key low temperature processes for a silicon-based 3D sequential integration

International audienc

Key low temperature processes for a silicon-based 3D sequential integration

International audienc

FDSOI for cryoCMOS electronics: device characterization towards compact model

International audienceWe present a status of FDSOI transistors electrical characterization for very low temperature operation. We highlight in particular singular transport and thermal effects occurring at low T. We also present the physical and analytical models associated with various characteristic electrical parameters, paving the way towards cryogenic compact models

A cost effective RF-SOI Drain Extended MOS transistor featuring PSAT=19dBm @28GHz & VDD=3V for 5G Power Amplifier application

International audienceA high voltage N-type Drain Extended MOS(NDEMOS) in 40nm RFSOI technology is presented for PA application. After a careful optimization of the drain extension,the NDEMOS transistor exhibits a fT.BV>700 GHz.V & fMAX=205GHz at Lg=70nm & VDD=2V, that meet the PArequirements at mmW frequency. The large-signal RF performance of a common-source NDEMOS PA cell areassessed. It exhibits 19.2dBm of PSAT @VDD=3V, that may be further improved in a cascode configuration. With thisNDEMOS device, this 300mm SOIMMW technology becomes a very cost effective platform for Front End modules(FEM) that can be competitive with other CMOS technologies