A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms *

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CLT in Functional Linear Regression Models

International audienceWe propose in this work to derive a CLT in the functional linear regression model to get confidence sets for prediction based on functional linear regression. The main difficulty is due to the fact that estimation of the functional parameter leads to a kind of ill-posed inverse problem. We consider estimators that belong to a large class of regularizing methods and we first show that, contrary to the multivariate case, it is not possible to state a CLT in the topology of the considered functional space. However, we show that we can get a CLT for the weak topology under mild hypotheses and in particular without assuming any strong assumptions on the decay of the eigenvalues of the covariance operator. Rates of convergence depend on the smoothness of the functional coefficient and on the point in which the prediction is made

Holistic methodology for designing ultra high-speed SHA-1 hashing cryptographic module in hardware

Nowadays security is a critical issue as long as electronic transactions are concerned. Moreover taking into consideration the rapid growth of e-commerce and the future needs, it is essential to achieve higher throughput rates for the incorporated security schemes. The most common components in such security schemes are a cipher block and a hash function, with the second one being hard to compete with the throughput achieved by cipher blocks. In this paper a top-down methodology is presented which manages to increase throughput of SHA-1 hash function hardware design about 160% comparing to conventional implementations with a minor area penalty. © 2008 IEEE

Implementation of HSSec: A high-speed cryptographic co-processor

In this paper a high-speed cryptographic co-processor, named HSSec, is presented. The core embeds two hash functions, SHA-1 and SHA-512, and the symmetric block cipher AES. The architecture of HSSec renders it suitable for widely spread applications with security demands. The presented co-processor can be used inevery system integrating standards such as IPSec or the upcoming JPSec and P1619. The main characteristic of the proposed implementation is common use of the available resources, to minimize further area requirements. Additionally the cryptographic primitives can operate in parallel, providing high throughput whenever needed. Finally the system can operate in ECB or CBC modes. The HSSec co-processor has relatively small area and its performance reaches 1 Gbps (AES, SHA-1 and SHA-512) for XILINX's Virtex II FPGA family. © 2007 IEEE