Pavlov's dog associative learning demonstrated on synaptic-like organic transistors

In this letter, we present an original demonstration of an associative learning neural network inspired by the famous Pavlov's dogs experiment. A single nanoparticle organic memory field effect transistor (NOMFET) is used to implement each synapse. We show how the physical properties of this dynamic memristive device can be used to perform low power write operations for the learning and implement short-term association using temporal coding and spike timing dependent plasticity based learning. An electronic circuit was built to validate the proposed learning scheme with packaged devices, with good reproducibility despite the complex synaptic-like dynamic of the NOMFET in pulse regime

Symphonie massively parallel computer, modelling and design

The goal of this paper is to present an embedded calculator for image processing SYMPHONIE and the methodology used for its realization. In this calculator we could have up to 1024 processors . Its first application will take place in the french Rafale Aircraft as core of the infra-red system . For this application, low size and low consumption will be very important and an ASIC of a million gates has been developped . To succeed in this realization we used a VHDL model allowing simulations on the full system . Then we used VHDL synthesis methods for the conception of the ASIC . We will conclude this paper by a presentation of some perfomances of the system in some applications fields .L'objectif de cet article est de présenter le calculateur embarqué de traitement d'image SYMPHONIE, ainsi que la méthodologie mise en oeuvre pour sa réalisation. Ce calculateur dont une des applications se situe au coeur du système de veille infrarouge de l'avion Rafale pourra comporter jusqu'à 1024 processeurs. Afin de tenir compte des contraintes de volume et de consommation, un ASIC d'un million de portes a été développé. Pour réussir cette réalisation un modèle VHDL a été écrit permettant des simulations de l'ensemble du système. Par ailleurs, ce modèle a permis d'aborder la réalisation du circuit ASIC en faisant appel aux outils de synthèse VHDL. Nous terminerons cette présentation par quelques performances dans différents domaines d'applications

Memristive based device arrays combined with Spike based coding can enable efficient implementations of embedded neuromorphic circuits

Conference of 61st IEEE International Electron Devices Meeting, IEDM 2015 ; Conference Date: 7 December 2015 Through 9 December 2015; Conference Code:119534International audienceSince the rapid development of post-CMOS technologies in the last decade, there has been a growing interest in utilizing them for implementing neuromorphic or brain-like computing machines. Besides attempts to build realistic circuits that would mimic the functioning of biological neurons as close as possible [1][2], our team is focused on implementing neuromorphic circuits suitable for embedded applications. This objective puts the emphasis on two majors concerns: integration and energy efficiency. In our quest for ultimate integration, we first report on investigating for the best synapse-like technology among the realm of potential candidates. We then report our investigations on the feasibility of large crossbars of synapse-like devices and show that there is still a long way ahead. Finally in an effort to tackle the energy problem, we introduce spike based coding for deep neuromorphic architectures and discuss our argument that spike coding combined with memristive synaptic devices could pave the way for future embedded neuromorphic circuits

Theoretical analysis of spike-timing-dependent plasticity learning with memristive devices

International audienceSeveral recent works, described in chapters of the present series, have shown that memristive devices can naturally emulate variations of the biological spike-timing-dependent plasticity (STDP) learning rule and can allow the design of learning systems. Such systems can be built with memristive devices of extremely diverse physics and behaviors and are particularly robust to device variations and imperfections. The present work investigates the theoretical roots of their STDP learning. It is suggested, by revisiting works developed in the field of computational neuroscience, that STDP learning can approximate the machine learning algorithm of Expectation-Maximization, the neural network operation implementing “Expectation” steps, while STDP itself implementing “Maximization” steps. This process allows a system to perform Bayesian inference among the values of a latent variable present in the input. This theoretical analysis allows interpreting how STDP differs for several device physics and why it is robust to devicemismatch. It can also provide guidelines for designing STDP-based learning systems. � Springer (India) Pvt. Ltd. 2017

Design exploration methodology for memristor-based spiking neuromorphic architectures with the Xnet event-driven simulator

International audience—We introduce an event-based methodology, and its accompanying simulator (" Xnet ") for memristive nanodevice-based neuromorphic hardware, which aims to provide an intermediate modeling level, between low-level hardware description languages and high-level neural networks simulators used primarily in neurosciences. This simulator was used to establish several results on Spike-Timing-Dependent Plasticity (STDP) modeling and implementation with Resistive RAM (RRAM), Conductive Bridge RAM (CBRAM) and Phase-Change Memory (PCM) type of memristive nanodevices. We present several simulation case studies that illustrate the event-based simulation strategies that we implemented, including unsupervised features extraction and Monte Carlo simulations. A discussion comparing event-based and fixed time-step simulation is included as well, and gives some metrics to guide the choice between the two depending on the application to simulate

Sneak paths effects in CBRAM memristive devices arrays for spiking neural networks

Conference of 2014 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2014 ; Conference Date: 8 July 2014 Through 10 July 2014; Conference Code:107210International audienceIn this paper, we study the effects of sneak paths and parasitic metal line resistance in arrays of CBRAM memristive devices operating as synapses for spiking neural networks. Three structures of crosspoint array are reviewed: the crossbar (1R), the anode connected matrix (1T-IR) and the cathode connected matrix (1T-IR). We show that the crossbar is an energy-consuming structure with high leakage during SET/RESET and with an increased switching time due to voltage drops along the lines. Furthermore, we show that parasitic line resistance can have a significant impact on the read resistance of the devices, depending on their location in the crossbar

Design study of efficient digital order-based STDP neuron implementations for extracting temporal features

Conference of 2013 International Joint Conference on Neural Networks, IJCNN 2013 ; Conference Date: 4 August 2013 Through 9 August 2013; Conference Code:102436International audienceSpiking neural networks are naturally asynchronous and use pulses to carry information. In this paper, we consider implementing such networks on a digital chip. We used an event-based simulator and we started from a previously established simulation, which emulates an analog spiking neural network, that can extract complex and overlapping, temporally correlated features. We modified this simulation to allow an easier integration in an embedded digital implementation. We first show that a four bits synaptic weight resolution is enough to achieve the best performance, although the network remains functional down to a 2 bits weight resolution. Then we show that a linear leak could be implemented to simplify the neurons leakage calculation. Finally, we demonstrate that an order-based STDP with a fixed number of potentiated synapses as low as 200 is efficient for features extraction. A simulation including these modifications, which lighten and increase the efficiency of digital spiking neural network implementation shows that the learning behavior is not affected, with a recognition rate of 98% in a cars trajectories detection application

Probabilistic neuromorphic system using binary phase-change memory (PCM) synapses: Detailed power consumption analysis

Conference of 2013 13th IEEE International Conference on Nanotechnology, IEEE-NANO 2013 ; Conference Date: 5 August 2013 Through 8 August 2013; Conference Code:102723International audienceIn this paper we investigate the use of phase-change memory (PCM) devices as binary probabilistic synapses in a neuromorphic computing system for complex visual pattern extraction. Different PCM programming schemes for architectures with- or without-selector devices are provided. The functionality of the system is tested through large-scale neural network simulations. The system-level simulations show that such a system can solve a complex real-life video processing problem (vehicle counting) with high recognition rate (>94%) and low power consumption. The impact of the resistance window on the power consumption of the system is also studied. Results show that the learning-mode power consumption can be dramatically reduced if the RESET state of the PCM devices is tuned to a relatively low resistance. Read-mode power consumption, on the other hand, can be minimized by increasing the resistance values for both SET and RESET states of the PCM devices