Экспрессный контроль надежности подзатворного диэлектрика полупроводниковых приборов

The key element determining stability of the semiconductor devices is a gate dielectric. As its thickness reduces in the process of scaling the combined volume of factors determining its electrophysical properties increases. The purpose of this paper is development of the control express method of the error-free running time of the gate dielectric and study the influence of the rapid thermal treatment of the initial silicon wafers and gate dielectric on its reliability.The paper proposes a model for evaluation of the reliability indicators of the gate dielectrics as per the trial results of the test MDS-structures by means of applying of the ramp-increasing voltage on the gate up to the moment of the structure breakdown at various velocities of the voltage sweep with measurement of the IV-parameters. The proposed model makes it possible to realize the express method of the reliability evaluation of the thin dielectrics right in the production process of the integrated circuits.On the basis of this method study of the influence of the rapid thermal treatment of the initial silicon wafers of the KEF 4.5, KDB 12 wafers and formed on them by means of the pyrogenic oxidation of the gate dielectric for the error-free running time were performed. It is shown, that rapid thermal treatment of the initial silicon wafers with their subsequent oxidation results in increase of the error-free running time of the gate dielectric on average from 12.9 to 15.9 years (1.23 times greater). Thermal treatment of the initial silicon wafers and gate dielectric makes it possible to expand the error-free running time up to 25.2 years, i.e.1.89 times more, than in the standard process of the pyrogenic oxidation and 1.5 times more, than under application of the rapid thermal treatment of the initial silicon wafers only.Ключевым элементом, определяющим стабильность полупроводниковых приборов, является подзатворный диэлектрик. По мере уменьшения его толщины в процессе масштабирования растет совокупный объем факторов, определяющих его электрофизические свойства. Целью данной работы являлась разработка экспрессного метода контроля времени наработки на отказ подзатворного диэлектрика и исследование влияния быстрой термической обработки исходных кремниевых пластин и подзатворного диэлектрика на его надежность.В работе предложен метод оценки показателей надежности подзатворных диэлектриков по результатам испытаний тестовых МДП-структур путем подачи на затвор ступенчато-нарастающего напряжения до фиксации момента пробоя структуры при разных скоростях развертки напряжения при измерении вольт-амперных характеристик. Предложенная модель позволяет реализовать экспрессный метод оценки надежности тонких диэлектриков непосредственно в процессе производства кристаллов микросхем.На основании данного метода проведены исследования влияния быстрой термической обработки исходных кремниевых пластин КЭФ 4,5, КДБ 12 и сформированного на них путем пирогенного окисления подзатворного диэлектрика на время наработки его на отказ. Показано, что быстрая термическая обработка исходных кремниевых пластин с последующим их пирогенным окислением приводит к увеличению времени наработки на отказ подзатворного диэлектрика в среднем с 12,9 до 15,9 года (в 1,23 раза). Термообработка исходных кремниевых пластин и подзатворного диэлектрика позволяет увеличить время наработки на отказ до 25,2 года, т.е. в 1,89 раза больше, чем при стандартном процессе пирогенного окисления, и в 1,5 раза больше, чем при применении быстрой термообработки только исходных кремниевых пластин

Reliability Express Control of the Gate Dielectric of Semiconductor Devices

The key element determining stability of the semiconductor devices is a gate dielectric. As its thickness reduces in the process of scaling the combined volume of factors determining its electrophysical properties increases. The purpose of this paper is development of the control express method of the error-free running time of the gate dielectric and study the influence of the rapid thermal treatment of the initial silicon wafers and gate dielectric on its reliability.The paper proposes a model for evaluation of the reliability indicators of the gate dielectrics as per the trial results of the test MDS-structures by means of applying of the ramp-increasing voltage on the gate up to the moment of the structure breakdown at various velocities of the voltage sweep with measurement of the IV-parameters. The proposed model makes it possible to realize the express method of the reliability evaluation of the thin dielectrics right in the production process of the integrated circuits.On the basis of this method study of the influence of the rapid thermal treatment of the initial silicon wafers of the KEF 4.5, KDB 12 wafers and formed on them by means of the pyrogenic oxidation of the gate dielectric for the error-free running time were performed. It is shown, that rapid thermal treatment of the initial silicon wafers with their subsequent oxidation results in increase of the error-free running time of the gate dielectric on average from 12.9 to 15.9 years (1.23 times greater). Thermal treatment of the initial silicon wafers and gate dielectric makes it possible to expand the error-free running time up to 25.2 years, i.e.1.89 times more, than in the standard process of the pyrogenic oxidation and 1.5 times more, than under application of the rapid thermal treatment of the initial silicon wafers only

Localized plasmon resonance in boron-doped multiwalled carbon nanotubes

Substitutionally boron-doped multiwalled carbon nanotubes (B-CNTs) with lengths mainly less than 0.5 μ m and diameters 10–30 nm have been obtained by arc-discharge evaporation of the graphite anode containing boron material. The broad peak has been observed in the midinfrared conductivity spectra of the thin film comprising B-CNTs. The peak was suggested to be associated with a phenomenon known as localized plasmon resonance. Theoretical analysis has been done to confirm the possibility of this phenomenon to occur in the B-CNTs