One-by-one trap activation in silicon nanowire transistors

Flicker or 1/f noise in metal-oxide-semiconductor field-effect transistors (MOSFETs) has been identified as the main source of noise at low frequency. It often originates from an ensemble of a huge number of charges trapping and detrapping. However, a deviation from the well-known model of 1/f noise is observed for nanoscale MOSFETs and a new model is required. Here, we report the observation of one-by-one trap activation controlled by the gate voltage in a nanowire MOSFET and we propose a new low-frequency-noise theory for nanoscale FETs. We demonstrate that the Coulomb repulsion between electronically charged trap sites avoids the activation of several traps simultaneously. This effect induces a noise reduction by more than one order of magnitude. It decreases when increasing the electron density in the channel due to the electrical screening of traps. These findings are technologically useful for any FETs with a short and narrow channel.Comment: One file with paper and supplementary informatio

Electron-Shading Characterization in a HDP Contact Etching Process Using a Patterned CHARM Wafer

In this work, a CHARM-2 wafer with high aspect ratio resist patterns has been used to quantitatively I. Introduction To understand the origin of plasma-induced damage, useful plasma parameters such as floating potentials and J-V characteristics can be measured using the non-invasive CHARM method To study this effect, we have designed different resist patterns on a 200 mm CHARM™-2 wafer with an e-beam lithography. This allows to obtain realistic variable aspect ratio as high as 4, contrary to previous studie

Assessing the correlation between location and size of catastrophic breakdown events in high-K MIM capacitors

The connection between the spatial location of catastrophic breakdown spots occurring in metal-insulator-metal capacitors with a high-permittivity dielectric film (HfO 2 ) and their respective sizes is investigated. Large area structures (10 4 -10 5 μm 2 ) are used for this correlation assessment since, for statistical considerations, a large number of spots in the same device is imperatively required. The application of ramped or constant voltage stress across the capacitor generates defects inside the dielectric that result in the formation of multiple failure sites. High power dissipation takes place locally, leaving a permanent mark on the top electrode of the device. The set of marks constitutes a point pattern with attributes that can be analyzed from a statistical viewpoint. The correlation between the spot locations and their sizes is assessed through the mark correlation function and the method of reverse conditional moments. The study reveals that for severely damaged devices, there exists a link between the spot location and size that leads to a short range departure from a complete spatial randomness (CSR) process. It is shown that the affected region around each failure site is actually larger than the visible area of the spot. A structural modification of the dielectric layer in the vicinity of the spot caused by the huge thermal effects occurring just before the microexplosion might be the reason behind this extension of the damage

Accurate determination of flat band voltage in advanced MOS structure

International audienc

Accurate determination of flat band voltage in advanced MOS structure

International audienc

Accurate determination of flat band voltage in advanced MOS structure

International audienc