The Effect of High Temperature Annealing on Fluorine Distribution Profile and Electro-Physical Properties of Thin Gate Oxide Fluorinated by Silicon Dioxide RIE in CF4 Plasma, Journal of Telecommunications and Information Technology, 2010, nr 1

This study describes the effects of high temperature annealing performed on structures fluorinated during initial silicon dioxide reactive ion etching (RIE) process in CF4 plasma prior to the plasma enhanced chemical vapour deposition (PECVD) of the final oxide. The obtained results show that fluorine incorporated at the PECVD oxide/Si interface during RIE is very stable even at high temperatures. Application of fluorination and high temperature annealing during oxide layer fabrication significantly improved the properties of the interface (DitmDitmb decreased), as well as those of the bulk of the oxide layer (Qef f decreased). The integrity of the oxide (higher Vbd ) and its uniformity (Vbd distribution) are also improved

Novel Method of Improving Electrical Properties of Thin PECVD Oxide Films by Fluorination of Silicon Surface Region by RIE in RF CF4 Plasma, Journal of Telecommunications and Information Technology, 2010, nr 1

This study describes a novel technique to form good quality low temperature oxide (< 350◦C). Low temperature oxide was formed by N2O + SiH4:N2 plasma in a plasma enhanced chemical vapour deposition (PECVD) system on the silicon surface reactively etched in CF4 plasma (RIE – reactive ion etching). The fabricated oxide demonstrated excellent (for low temperature dielectric formation process) currentvoltage (I−V) characteristics, such as: low leakage current, high breakdown voltage and good reliability. Experimental results indicate that the proposed method of fluorine incorporation into the SiO2/Si inteface improves electrical parameters of MOS structures

Charge-pumping characterization of FILOX vertical MOSFETs, Journal of Telecommunications and Information Technology, 2007, nr 3

This paper presents for the first time the results of charge-pumping (CP) measurements of FILOX vertical transistors. The aim of these measurements is to provide information on the density of interface traps at the Si-SiO2 interface fabricated in a non-standard process. Flat-band and threshold voltage, as well as density of interface traps are determined. Good agreement between threshold-voltage values obtained from CP and I-V measurements is observed

Applying shallow nitrogen implantation from rf plasma for dual gate oxide technology, Journal of Telecommunications and Information Technology, 2007, nr 3

The goal of this work was to study nitrogen implantation from plasma with the aim of applying it in dual gate oxide technology and to examine the influence of the rf power of plasma and that of oxidation type. The obtained structures were examined by means of ellipsometry, SIMS and electrical characterization methods

Charge-pumping characterization of SOI devices fabricated by means of wafer bonding over pre-patterned cavities, Journal of Telecommunications and Information Technology, 2007, nr 3

The quality of the silicon-buried oxide bonded interface of SOI devices created by thin Si film transfer and bonding over pre-patterned cavities, aiming at fabrication of DG and SON MOSFETs, is studied by means of chargepumping (CP) measurements. It is demonstrated that thanks to the chemical activation step, the quality of the bonded interface is remarkably good. Good agreement between values of front-interface threshold voltage determined from CP and I-V measurements is obtained

The influence of annealing (900◦C) of ultra-thin PECVD silicon oxynitride layers, Journal of Telecommunications and Information Technology, 2007, nr 3

This work reports on changes in the properties of ultra-thin PECVD silicon oxynitride layers after high- temperature treatment. Possible changes in the structure, composition and electrophysical properties were investigated by means of spectroscopic ellipsometry, XPS, SIMS and electrical characterization methods (C-V, I-V and charge- pumping). The XPS measurements show that SiOxNy is the dominant phase in the ultra-thin layer and high-temperature annealing results in further increase of the oxynitride phase up to 70% of the whole layer. Despite comparable thickness, SIMS measurement indicates a densification of the annealed layer, because sputtering time is increased. It suggests complex changes of physical and chemical properties of the investigated layers taking place during high-temperature annealing. The C-V curves of annealed layers exhibit less frequency dispersion, their leakage and charge-pumping currents are lower when compared to those of as-deposited layers, proving improvement in the gate structure trapping properties due to the annealing process

FOSS EKV2.6 Verilog-A Compact MOSFET Model

The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. The model is available as a free open-source software (FOSS) tool coded in Verilog-A. The present paper provides a short review of foundations of the model and shows its capabilities via characterization and modeling based on a test chip in 180 nm CMOS fabricated via Europractice