PV Cell Characteristic Extraction to Verify Power Transfer Efficiency in Indoor Harvesting System

A method is proposed to verify the efficiency of low-power harvesting systems based on Photovoltaic (PV) cells for indoor applications and a Fractional Open-Circuit Voltage (FOCV) technique to track the Maximum Power Point (MPP). It relies on an algorithm to reconstruct the PV cell Power versus Voltage (P-V) characteristic measuring the open circuit voltage and the voltage/current operating point but not the short-circuit current as required by state-of-the-art algorithms. This way the characteristic is reconstructed starting from the two values corresponding to standard operation modes of dc-dc converters implementing the FOCV Maximum Power Point Tracking (MPPT) technique. The method is applied to a prototype system: an external board is connected between the transducer and the dc-dc converter to measure the open circuit voltage and the voltage/current operating values. Experimental comparisons between the reconstructed and the measured P-V characteristics validate the reconstruction algorithm. Experimental results show the method is able to clearly identify the error between the transducer operating point and the one corresponding to the maximum power transfer, whilst also suggesting corrective action on the programmable factor of the FOCV technique. The proposed technique therefore provides a possible way of estimating MPPT efficiency without sampling the full P-V characteristic

A gated oscillator clock and data recovery circuit for nanowatt wake-up and data receivers

This article presents a data-startable baseband logic featuring a gated oscillator clock and data recovery (GO-CDR) circuit for nanowatt wake-up and data receivers (WuRxs). At each data transition, the phase misalignment between the data coming from the analog front-end (AFE) and the clock is cleared by the GO-CDR circuit, thus allowing the reception of long data streams. Any free-running frequency mismatch between the GO and the bitrate does not limit the number of receivable bits, but only the maximum number of equal consecutive bits (Nm). To overcome this limitation, the proposed system includes a frequency calibration circuit, which reduces the frequency mismatch to ±0.5%, thus enabling the WuRx to be used with different encoding techniques up to Nm = 100. A full WuRx prototype, including an always-on clockless AFE operating in subthreshold, was fabricated with STMicroelectronics 90 nm BCD technology. The WuRx is supplied with 0.6 V, and the power consumption, excluding the calibration circuit, is 12.8 nW during the rest state and 17 nW at a 1 kbps data rate. With a 1 kbps On-Off Keying (OOK) modulated input and −35 dBm of input RF power after the input matching network (IMN), a 10^(−3) missed detection rate with a 0 bit error tolerance is measured, transmitting 63 bit packets with the Nm ranging from 1 to 63. The total sensitivity, including the estimated IMN gain at 100 MHz and 433 MHz, is −59.8 dBm and −52.3 dBm, respectively. In comparison with an ideal CDR, the degradation of the sensitivity due to the GO-CDR is 1.25 dBm. False alarm rate measurements lasting 24 h revealed zero overall false wake-ups

Sintesi di frequenza in tecnologia CMOS per ricetrasmettitori Ultra Wide Band di tipo multi-band OFDM

L'attivit\ue0 si inquadra progetto PRIN dal titolo "Blocchi abilitanti per l'integrazione in tecnoogia CMOS di un ricetrasmettitore Ultra Wide Band del tipo multi-band OFDM" con responsabile nazionale il Prof. R.Castello dell'Universit\ue0 di Pavia. Obiettivo generale della ricerca \ue8 dimostrare, attraverso la realizzazione di prototipi, la fattibilit\ue0 dei blocchi circuitali pi\uf9 critici di un ricetrasmettitore UWB in tecnologia CMOS fortemente scalata. In questo contesto, l'attivit\ue0 dell'unit\ue0 di Bologna consiste nello studio di schemi architetturali e circuitali per la sintesi di frequenza

Sintesi di frequenza in tecnologia CMOS per ricetrasmettitori Ultra Wide Band di tipo multi-band OFDM

L'attivit\ue0 si inquadra progetto PRIN dal titolo "Blocchi abilitanti per l'integrazione in tecnoogia CMOS di un ricetrasmettitore Ultra Wide Band del tipo multi-band OFDM" con responsabile nazionale il Prof. R.Castello dell'Universit\ue0 di Pavia. Obiettivo generale della ricerca \ue8 dimostrare, attraverso la realizzazione di prototipi, la fattibilit\ue0 dei blocchi circuitali pi\uf9 critici di un ricetrasmettitore UWB in tecnologia CMOS fortemente scalata. In questo contesto, l'attivit\ue0 dell'unit\ue0 di Bologna consiste nello studio di schemi architetturali e circuitali per la sintesi di frequenza

3D visualization of convection patterns in lab-on-chip with open microfluidic outlet

Open-outlet microfluidics is getting more and more attention, thanks to the generation of capillarity-driven flows which simplify the connection with the macroworld. It is known that convection flows are generated at the interface with air, i.e., the meniscus. Several works have investigated evaporation-induced convection, but its effect on particle position control in open-outlet biodevices is still not characterized. In this paper, we present the results of 3D measurement of particle traces near the meniscus in an open-outlet vertical 400 lm micro-channel filled with a water-based saline solution. Using a standard optical microscope and a system of mirrors, we observe the 3D position of individual micro-beads floating in the solution, in a way akin to particle image velocimetry technique. A single vortex is generated at the meniscus and occupies the whole region under observation at a distance of 1.5–2.7 mm from the meniscus. The generation of the convection pattern and the vortex rotational speed are described. The convection patterns disappear when evaporation is inhibited, while both the vortex generation and the rotational speed are faster for highly saline solutions. These results are relevant to the design of biochips which require control of the particle position in a fluid since they emphasize that in open-outlet microfluidic systems not only the gravitational fall but also the convection drag must be counteracted

Electronic Microsystems for Handling of Rare Cells

This review paper summarizes some of the most challenging issues regarding the development of electronic microsystems for the isolation, manipulation, and characterization of rare cells. Two relevant areas, namely, immunology for cancer therapy and monitoring of microbial contaminants in water, are presented as example applications which require handling of rare cells. Starting from these applications, the state of the art in electronic microsystem research is presented, and various solutions are discussed, highlighting the advantages and disadvantages of each technology and suggesting the need to integrate multiple solutions to meet the application requirements

On the simulation of fast settling charge pump PLLs up to fourth order

In this paper, we discuss three different models for the simulation of integer-N charge-pump phase-locked loops (PLLs), namely the continuous-time s-domain and discrete time z-domain approximations and the exact semi-analytical time-domain model. The limitations of the two approximated models are analyzed in terms of error in the computed settling time as a function of loop parameters, deriving practical conditions under which the different models are reliable for fast settling PLLs up to fourth order. Besides, output spectral purity analysis methods based upon the time-domain model are introduced and the results are compared with those obtained by means of the s-domain model in terms of phase noise and reference spur estimation. As a case study, we use the three models to analyze a fast switching PLL to be integrated in a frequency synthesizer for WiMedia MB-OFDM UWB systems

A CMOS 90 nm 55 mW 3.4-to-9.2 GHz 12 Band frequency synthesizer for MB-OFDM UWB

A frequency synthesizer for UWB MB-OFDM applications is designed in TSMC 90 nm CMOS technology. It is based on two wideband PLLs capable of settling in less than 300 ns with a 66 MHz external reference. The PLL tuning range (6.6–9.2 GHz) is extended down to 3.4 GHz by a dedicated circuit able to divide the output frequency by 1, 1.5 and 2 with a power consumption of less than 3 mW. Measured data fit the UWB MB-OFDM specifications with an integrated phase noise of 2.8° RMS at maximum output frequency and an aggregate spurious tone power of less than 27 dBc. The joint power consumption is 55 mW and the synthesizer core area occupies less than 0.5 mm2