Efficient Data Pipelines for Combined FPGA/APU Systems

A common architecture for COTS payload computers in space applications combines a COTS APU (CPU+GPU combo) with an FPGA. The FPGA provides monitoring, Triple Modular Redundancy (TMR), and other space-suitable properties, while the APU serves as the high-performance compute component. The FPGA can also be utilized for custom interfaces and tasks it excels at, such as certain real-time operations

Smart On-board Processing for Next Generation SAR Payloads

Smart on-board processing for Earth observation systems (SOPHOS) is a 3-year Horizon Europe project. SOPHOS will design and implement enabling technology for high-end data products produced on board spacecraft via the implementation of more power efficient high-performance space processing chains for various Low-Earth Orbit (LEO) missions, with a focus on Synthetic Aperture Radar (SAR), which is one of the most data intensive space applications currently used. This paper describes the adopted technology and the selected SAR use cases

En studie i konfigurerbar hårdvaruaccelerering för CABAC i flerstandards mediabearbetning

To achieve greater compression ratios new video and image CODECs like H.264 and JPEG 2000 take advantage of Context adaptive binary arithmetic coding. As it contains computationally heavy algorithms, fast implementations have to be made when they are performed on large amount of data such as compressing high resolution formats like HDTV. This document describes how entropy coding works in general with a focus on arithmetic coding and CABAC. Furthermore the document dicusses the demands of the different CABACs and propose different options to hardware and instruction level optimisation. Testing and benchmarking of these implementations are done to ease evaluation. The main contribution of the thesis is parallelising and unifying the CABACs which is discussed and partly implemented. The result of the ILA is improved program flow through a specialised branching operations. The result of the DHA is a two bit parallel accelerator with hardware sharing between JPEG 2000 and H.264 encoder with limited decoding support

SOPHOS - Smart Onboard Processing for Earth Observation Systems D1.1 - Use Cases, Applications and Technical Requirements Report

This document gives a description of the envisioned use cases and applications that are used as a foundation for the developments in the SOPHOS project. Additionally, the high-level requirements are derived from the reported use cases. This document starts with a survey of SAR applications and current missions and sensors. The survey covers both, institutional SAR missions (Copernicus program of the EC, national SAR missions like TerraSAR-X/TanDEM-X) and commercial activities (e.g. ICEYE). Parameters of a so-called SOPHOS reference SAR sensor are established to reflect the suspected very near future characteristics of an individual SAR sensor in a commercial constellation. For the design of the SOPHOS demonstrator we present a survey on the state-of-the-art and key enabling technologies. The document concludes with the summary of the high-level requirements to be met by the SOPHOS demonstrator