A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under simultaneous negative gate bias and illumination

It has been previously observed that thin film transistors (TFTs) utilizing an amorphous indium gallium zinc oxide (a-IGZO) semiconducting channel suffer from a threshold voltage shift when subjected to a negative gate bias and light illumination simultaneously. In this work, a thermalization energy analysis has been applied to previously-published data on negative bias under illumination stress (NBIS) in a-IGZO TFTs. A barrier to defect conversion is extracted of 0.65 – 0.75 eV, which is consistent with reported energies of oxygen vacancy migration. The attempt-to-escape frequency is extracted to be 106 – 107 s–1 which suggests a weak localization of carriers in band tail states over a 20 – 40 nm distance. Models for the NBIS mechanism based on charge trapping are reviewed and a defect pool model is proposed in which two distinct distributions of defect states exist in the a-IGZO band gap: these are associated with states that are formed as neutrally charged and 2+ charged oxygen vacancies at the time of film formation. In this model, threshold voltage shift is not due to a defect creation process, but to a change in the energy distribution of states in the band gap upon defect migration as this allows a state formed as a neutrally charged vacancy to be converted into one formed as a 2+ charged vacancy and vice versa. Carrier localization close to the defect migration site is necessary for the conversion process to take place, and such defect migration sites are associated with conduction and valence band tail states. Under negative gate bias stressing, the conduction band tail is depleted of carriers, but the bias is insufficient to accumulate holes in the valence band tail states, and so no threshold voltage shift results. It is only under illumination that the quasi Fermi level for holes is sufficiently lowered to allow occupation of valence band tail states. The resulting charge localization then allows a negative threshold voltage shift, but only under conditions of simultaneous negative gate bias and illumination, as observed experimentally as the NBIS effect.This work was supported by the European Community’s 7th Framework Programme under grant agreement NMP3-LA-2010-246334.Copyright 2014 American Institute of Physics. This article may be downloaded for personal use only. Any other use requires prior permission of the author and the American Institute of Physics

An Approach to Simultaneously Test Multiple Devices for High-Throughput Production of Thin-Film Electronics

New generation of thin-film transistors (TFTs), where the active material is amorphous oxide, conjugated polymer, or small molecules, have the advantage of flexibility, high form factor, and large scale manufacturability through low cost processing techniques, e.g., roll-to-roll printing, screen printing. During high-throughput production using these techniques, the probability of defects being present increases with the speed of manufacturing and area of devices. Therefore a high-throughput and low cost testing technique is absolute essential to maintain high quality of final product. We report a Simultaneous Multiple Device Testing (SMuDT) approach which is up to 10 times faster and cost effective than conventional testing methods. The SMuDT approach was validated using circuit simulation and demonstrated by testing large scale indium gallium zinc oxide (IGZO) TFTs. A method to ‘bin’ the tested devices using Figure of Merit was established.The authors acknowledge the support of this project provided by the EPSRC and Innovate UK through the AUTOFLEX Project (grant no. EP/L505201/1) and CIMLAE Project (EP/K03099X/1). AK and AJF would like to thank PragmatIC Printing Ltd. for wafer samples. Additional data related to this publication which is not of a commercially sensitive nature is available at the DSpace@Cambridge data repository (www.repository.cam.ac.uk).This is the final version of the article. It first appeared from IEEE via http://dx.doi.org/10.1109/JDT.2015.246229

On-chip temperature-compensated Love mode surface acoustic wave device for gravimetric sensing

Love mode surface acoustic wave (SAW) sensors have been recognized as one of the most sensitive devices for gravimetric sensors in liquid environments such as bio sensors. Device operation is based upon measuring changes in the transmitted (S21) frequency and phase of the first-order Love wave resonance associated with the device upon on attachment of mass. However, temperature variations also cause a change in the first order S21 parameters. In this work, shallow grooved reflectors and a ‘dotted’ single phase unidirectional interdigitated transducer (D-SPUDT) have been added to the basic SAW structure which promote unidirectional Love wave propagation from the device’s input interdigitated transducers. Not only does this enhance the first-order S21 signal, but it also allows propagation of a third-order Love wave. The attenuation coefficient of the third-order wave is sufficiently great that, whilst there is a clear reflected S11 signal, the third-order wave does not propagate into the gravimetric sensing area of the device. As a result, whilst the third-order S11 signal is affected by temperature changes, it is unaffected by mass attachment in the sensing area. It is shown that this signal can be used to remove temperature effects from the first-order S21 signal in real time. This allows gravimetric sensing to take place in an environment without the need for any other temperature measurement or temperature control; this is a particular requirement of gravimetric biosensors.This is the accepted manuscript. The following article appeared in Applied Physics Letters and may be found at http://scitation.aip.org/content/aip/journal/apl/105/21/10.1063/1.4902989. Copyright 2014 American Institute of Physics. This article may be downloaded for personal use only. Any other use requires prior permission of the author and the American Institute of Physics

Stability under Gate Bias Stressing of Amorphous Oxide Thin Film Transistors

Stability of amorphous zinc tin oxide thin film transistors (TFTs) is investigated under positive bias stressing (PBS) at temperatures between 65 and 105 °C. The time and temperature dependence of the threshold voltage shift is analyzed using a thermalization energy concept. A maximum energy barrier to defect migration of 0.76 eV and the attempt-to-escape frequency of 10$^7$ s$^{-1}$ are extracted. These values are compared with those under PBS of amorphous indium gallium zinc oxide and hydrogenated amorphous silicon TFTs. The oxygen vacancy migration model that was proposed for amorphous oxide semiconductors is contrasted with the defect creation model that was proposed for amorphous silicon

Single-step fabrication of thin-film linear variable bandpass filters based on metal-insulator-metal geometry

A single-step fabrication method is presented for ultra-thin, linearly variable optical bandpass filters (LVBFs) based on a metal–insulator–metal arrangement using modified evaporation deposition techniques. This alternate process methodology offers reduced complexity and cost in comparison to conventional techniques for fabricating LVBFs. We are able to achieve linear variation of insulator thickness across a sample, by adjusting the geometrical parameters of a typical physical vapor deposition process. We demonstrate LVBFs with spectral selectivity from 400 to 850 nm based on Ag (25 nm) and MgF$_{2}$ (75–250 nm). Maximum spectral transmittance is measured at ∼70% with a $\textit{Q}$-factor of ∼20.Engineering and Physical Sciences Research Council (EPSRC) (EP/L015455/1); Cambridge Commonwealth, European and International Trust

Analysis of amorphous indium-gallium-zinc-oxide thin-film transistor contact metal using Pilling-Bedworth theory and a variable capacitance diode model

It is widely reported that threshold voltage and on-state current of amorphous indium-gallium-zinc-oxide bottom-gate thin-film transistors are strongly influenced by the choice of source/drain contact metal. Electrical characterisation of thin-film transistors indicates that the electrical properties depend on the type and thickness of the metal(s) used. Electron transport mechanisms and possibilities for control of the defect state density are discussed. Pilling-Bedworth theory for metal oxidation explains the interaction between contact metal and amorphous indium-gallium-zinc-oxide, which leads to significant trap formation. Charge trapping within these states leads to variable capacitance diode-like behavior and is shown to explain the thin-film transistor operation.This work was supported by the Engineering and Physical Sciences Research CouncilThis is the author's accepted manuscript of the publication: http://dx.doi.org/10.1063/1.480199

Effects of post-deposition vacuum annealing on film characteristics of p-type Cu2_{2}O and its impact on thin film transistor characteristics

Annealing of cuprous oxide (Cu$_{2}$O) thin films in vacuum without phase conversion for subsequent inclusion as the channel layer in p-type thin film transistors (TFTs) has been demonstrated. This is based on a systematic study of vacuum annealing effects on the sputtered p-type Cu$_{2}$O as well as the performance of TFTs on the basis of the crystallographic, optical, and electrical characteristics. It was previously believed that high-temperature annealing of Cu$_{2}$O thin films would lead to phase conversion. In this work, it was observed that an increase in vacuum annealing temperature leads to an improvement in film crystallinity and a reduction in band tail states based on the X-ray diffraction patterns and a reduction in the Urbach tail, respectively. This gave rise to a considerable increase in the Hall mobility from 0.14 cm$^{2}$/V·s of an as-deposited film to 28 cm$^{2}$/V·s. It was also observed that intrinsic carrier density reduces significantly from 1.8 × 1016 to 1.7 × 10$^{13}$ cm$^{-3}$ as annealing temperature increases. It was found that the TFT performance enhanced significantly, resulting from the improvement in the film quality of the Cu$_{2}$O active layer: enhancement in the field-effect mobility and the on/off current ratio, and a reduction in the off-state current. Finally, the bottom-gate staggered p-type TFTs using Cu$_{2}$O annealed at 700 °C showed a field-effect mobility of ∼0.9 cm$^{2}$/V·s and an on/off current ratio of ∼3.4 × 102.This work was supported by the Engineering and Physical Sciences Research Council under Grant No. EP/M013650/1. G.R. acknowledges the support of the Cambridge Trusts

Analysis of the Conduction Mechanism and Copper Vacancy Density in p-type Cu2_{2}O Thin Films

A quantitative and analytical investigation on the conduction mechanism in p-type cuprous oxide (Cu$_{2}$O) thin films is performed based on analysis of the relative dominance of trap-limited and grain-boundary-limited conduction. It is found that carrier transport in as-deposited Cu$_{2}$O is governed by grain-boundary-limited conduction (GLC), while after high-temperature annealing, GLC becomes insignificant and trap-limited conduction (TLC) dominates. This suggests that the very low Hall mobility of as-deposited Cu$_{2}$O is due to significant GLC, and the Hall mobility enhancement by high-temperature annealing is determined by TLC. Evaluation of the grain size and the energy barrier height at the grain boundary shows an increase in the grain size and a considerable decrease in the energy barrier height after high-temperature annealing, which is considered to be the cause of the significant reduction in the GLC effect. Additionally, the density of copper vacancies was extracted; this quantitatively shows that an increase in annealing temperature leads to a reduction in copper vacancies.The support of this work by the Engineering and Physical Sciences Research Council (EPSRC) through project EP/M013650/1 is acknowledged

The Origin of the High Off-State Current in p-Type Cu₂O Thin Film Transistors

There is a need for a good quality p-type accumulation-mode thin film transistor (TFT) using a metal oxide semiconducting channel. P-type cuprous oxide (Cu₂O) has been proposed as a suitable semiconductor, but such TFTs have suffered from unacceptably high off-state currents. This paper studies the main origin of this high off-state current. Capacitance-voltage (C-V) characteristics reveal the accumulation of minority carriers (electrons) in the off-state regime (i.e. for a positive gate voltage). The activation energy extracted from the temperature dependence of the drain current as a function of gate voltage shows an abrupt lowering of the activation energy and pinning of the Fermi energy in the off-state region, which is attributed to subgap states at 0.38 eV from the conduction band minimum. This suggests that an electron flow in the off-state causes the high off-state current in p-type Cu₂O TFTs and not an inability to deplete the channel of holes

Air Stable Indium-Gallium-Zinc-Oxide Diodes with a 6.4 GHz Extrinsic Cutoff Frequency Fabricated Using Adhesion Lithography

High speed rectifiers that can be fabricated at low cost whilst still maintaining a high performance are of interest for wireless communication applications. In this letter amorphous indium gallium zinc oxide (a-IGZO) has been used with adhesion lithography (a technique to create asymmetric planar electrodes separated by a nanogap) to fabricate high performance Schottky diode rectifiers. The diode area and junction capacitance can be significantly reduced using this technique, improving device cut-off frequencies. Devices of different widths have been fabricated showing rectification ratios between 103-104. Capacitances measured for devices of various sizes were all on the order of 0.1 pF. By applying ac signals to the diode and measuring the output voltage across a load resistor a cut-off frequency was found. a IGZO diodes with an extrinsic cut-off frequency of 6.4 GHz at a 15 dBM input power have been realized. The devices also show good air stability with little change in current-voltage characteristics after 12 months