A -1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology

A 4-core cluster fabricated in low power 28nm UTBB FD-SOI conventional well technology is presented. The SoC architecture enables the processors to operate 'on-demand' on a 0.44V (1.8MHz) to 1.2V (475MHz) supply voltage wide range and -1.2V to 0.9V body bias wide range achieving the peak energy efficiency of 60 GOPS/W, (419\u3bcW, 6.4MHz) at 0.5V with 0.5V forward body bias. The proposed SoC energy efficiency is 1.4x to 3.7x greater than other low-power processors with comparable performance

Etude de l'effet d'histoire et optimisation des circuits logiques en technologie SOI partiellement désertée 130 et 65nm

L'objectif de ce travail est de répondre aux problématiques de conception liées à l'effet d'histoire dans les technologies CMOS/SOI partiellement désertées 0.131.1m et 65nm. Une étude approfondie a permis de mettre en évidence les limitations des méthodes classiquement utilisées pour caractériser l'impact de cet effet d'histoire sur les temps de propagation des portes. A partir des méthodologies d'initialisation de la charge du substrat flottant développées dans ce mémoire, un outil dédié à la caractérisation industrielle des bibliothèques de cellules standard a été développé. Cet outil permet d'obtenir, en seulement deux simulations, une estimation des cas de propagation les plus lents et les plus rapides, incluant la dispersion en régime aléatoire. Les résultats obtenus par cet outil confèrent aux circuits synthétisés une robustesse optimale à l'effet d'histoire tout en garantissant une dégradation négligeable des performances. Enfin les principaux facteurs de gain de cette technologie sont évalués pour les nœuds 130nm et 65nm.GRENOBLE1-BU Sciences (384212103) / SudocSudocFranceF

A 2.5μW 0.0067mm 2 automatic back-biasing compensation unit achieving 50% leakage reduction in FDSOI 28nm over 0.35-to-1V V<inf>DD</inf> range

International audienceAchieving 50% Leakage Reduction in FDSOI 28nm over 0.35-1V VDD Range [Placeholder for Author List] [Placeholder for Affiliations] Worst-case design and post silicon tuning are well-established digital design practices reducing timing violations in presence of process, temperature, aging and voltage variations but they suffer from extra power consumption due to overdesign [1]. Adaptive voltage scaling (AVS) [2] and body bias modulation [1] are well-known strategies to dynamically ensure that the digital core can operate at a targeted frequency, even in the presence of delay degradation due to variations. In a multiple voltage islands context, AVS requires many integrated supply generators such as switched capacitor converters that need to be controlled accurately. Also, for a fine-grain compensation, level shifters are required impacting a lot the circuit performances. As FDSOI technology offers the ability of adjusting the transistor speed through high sensitivity (85mV/VBB) VTH tuning by acting on buried Nwell (NW) and Pwell (PW) voltages, back biasing generators have been investigated [3-5]. However, they require an external controller to reach the optimal Back Bias (BB) voltages (no self-adjustment) [3-4] and [5] has a non-negligible area overhead for sub-mm 2 digital core for a narrow compensation range limited to 0.35-0.45V VDD. We therefore propose a variation-aware BB Compensation unit (BBC) which dynamically self-adjusts the N-and P-MOS transistors BB voltages to maintain the target frequency with low-latency tuning (100µs) across wide ranges of supply voltage (0.35-1V) and temperature (-40-125°C). The very low reported area of 0.0067mm 2 makes it affordable for a small digital core area (0.1-2mm 2). Requiring only a reference frequency signal FTGT, the proposed self-operating BBC exhibits 2.5µW quiescent current without any external component. Compared to worst-case design strategy, BBC brings up to 50% leakage reduction @0.45VDD@120°C and reduces the energy per cycle up to 32% compared to worst case design. Providing a continuous BB voltage adjustment (continuous VTH tuning), the target frequency is maintained within a +3.5% accuracy

Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology

Environmental temperature variations, as well as process variations, have a detrimental effect on performance and reliability of embedded systems implemented with deep-sub micron technologies. This sensitivity significantly increases in ultra-low-power (ULP) devices that operate in near-threshold, due to the magnification of process variations and to the strong thermal inversion that affects advanced technology nodes. Supporting an extended range of reverse and forward body-bias, UTBB FD-SOI technology provides a powerful knob to compensate for such variations. In this work we propose a methodology to efficiently compensate, at run-time, these variations. The proposed method exploits on-line performance measurements by means of Process Monitoring Blocks (PMBs) coupled with on-chip low-power Body Bias Generators. We characterize the response of the PMBs versus the maximum achievable frequency of the system, deriving a predictive model able to estimate such frequency with an error of 3%. We apply this model to compensate Temperature-induced performance variations, estimating the maximum frequency with an error of 7%; we eliminate the error by adding an appropriate body-bias margin resulting in a worst case global power consumption overhead of 5%. As further improvement, we generalize the methodology to compensate also process variations, obtaining an error of 28% on the estimated maximum performance and compensating this error with an overhead of 17% on the global power consumption

Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters

Reconfigurable finite-impulse response (FIR) filters are one of the most widely implemented components in Internet of Things systems that require flexibility to support several target applications while consuming the minimum amount of power to comply with the strict design requirements of portable devices. Due to the significant power consumption in the multiplier components of the FIR filter, various techniques aimed at reducing the switching activity of these multipliers have been proposed in the literature. However, these techniques rarely exploit the flexibility on the algorithmic level, which can lead to additional benefits. In this paper, FIR filter multipliers are extensively characterized with power simulations, providing a methodology for the perturbation of the coefficients of baseline filters at the algorithm level to trade-off reduced power consumption for filter quality. The proposed optimization technique does not require any hardware overhead and it enables the possibility of scaling the power consumption of the filter at runtime, while ensuring the full baseline performance of any programmed filter whenever it is required. The analyzed FIR filters were fabricated in a 28nm FD-SOI test chip and measured at a near-threshold, 600mV supply voltage. For example, by carefully choosing slightly perturbed coefficients in a low-pass configuration, power savings of up to 33% are achieved when accepting a 3dB degradation on the stopband, as compared with the baseline implementation of the filter

Design methodology with body bias: From circuit to engineering

session: FDSOI Circuits 2International audienceIn this paper, a built-in Body Bias design methodology is proposed and implemented in two different contexts: the automotive industry and the IoT paradigm. As opposed to the traditional design strategy, the proposed methodology incorporates Body Bias in all design stages, from synthesis to engineering. Measurements performed in a leakage-driven ADAS product and a dual core application processor in 28nm UTBB-FDSOI technology confirm the effectiveness of the proposed methodology, achieving a 30% reduction in static power, 25% in dynamic power, 15% yield recovery, and a 4X frequency and 2X leakage spread reduction