61 research outputs found

    Evidence in peroneal nerve entrapment: A scoping review

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    peer reviewedBackground and purpose: Daily management of patients with foot drop due to peroneal nerve entrapment varies between a purely conservative treatment and early surgery, with no high-quality evidence to guide current practice. Electrodiagnostic (EDX) prognostic features and the value of imaging in establishing and supplementing the diagnosis have not been clearly established. Methods: We performed a literature search in the online databases MEDLINE, Embase, and the Cochrane Library. Of the 42 unique articles meeting the eligibility criteria, 10 discussed diagnostic performance of imaging, 11 reported EDX limits for abnormal values and/or the value of EDX in prognostication, and 26 focused on treatment outcome. Results: Studies report high sensitivity and specificity of both ultrasound (varying respectively from 47.1% to 91% and from 53% to 100%) and magnetic resonance imaging (MRI; varying respectively from 31% to 100% and from 73% to 100%). One comparative trial favoured ultrasound over MRI. Variable criteria for a conduction block (>20%–≥50) were reported. A motor conduction block and any baseline compound motor action potential response were identified as predictors of good outcome. Based predominantly on case series, the percentage of patients with good outcome ranged 0%–100% after conservative treatment and 40%−100% after neurolysis. No study compared both treatments. Conclusions: Ultrasound and MRI have good accuracy, and introducing imaging in the standard diagnostic workup should be considered. Further research should focus on the role of EDX in prognostication. No recommendation on the optimal treatment strategy of peroneal nerve entrapment can be made, warranting future randomized controlled trials. © 2021 European Academy of Neurolog

    An Improved Definition of Synergistic and Antagonistic Effects

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    Deph profiling on Ta2O5 thin layer on Ta foil by ion scattering spectrometry

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    Proton Magnetic Resonance Spectroscopy of Thiocarbamate Herbicides

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    Exploring learning techniques for edge AI taking advantage of NVMs

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    International audienceThe relatively recent development and remarkable results of Artificial Neural Networks (ANNs) are dueto the construction of gigantic databases and algorithmic innovations requiring large hardware resources, which results in equally substantial energy consumptions. As Artificial Intelligence (AI) is now being embedded more and more into various connected objects, ranging from medical implants to autonomous cars, it is clear that the algorithmic and hardware solutions available in data centres will not be able to cover all the AI integration needs. The field of microelectronics has been working for several years now on the development of emerging memory technologies with the aim of integrating Non-Volatile Memory (NVM) within computing units. In a conventional processor architecture, such co-integration between the computation units and the memory would simplify the memory hierarchy, but also increase the bandwidth between computation and data access. In this study, we explore the potential of two non-volatile memory technologies, HfO2-based FeRAM [1] and OxRAM [2], for enabling on-chip learning systems. Notably, the quasi-infinite reading endurance of OxRAM devices and their poor writing endurance makes them suitable for inference-only applications, whereas the reported large writing endurance of FeRAM device would effectively allow moving training on-chip as well. Eventually, the migration of inference and learning from data centres to edge devices will allow them to adapt to the evolution of input data, to specialize each device to its user, to retain private data and offer faster service.To validate the feasibility of this approach, we designed a test chip in the 22nm FDSOI technology node.The primary objective of this chip is to demonstrate the implementation of a hybrid FeRAM/OxRAMmemory circuit capable of storing the synaptic weights of a Neural Network (NN) duringlearning/inference phases, while accelerating NN training at the edge. Eventually, by incorporatingsynaptic metaplasticity in Binarized Neural Networks [3], the chip addresses the issue of catastrophicforgetting. The chip consists of two sub-cores, each comprising four 16kbit FeRAM arrays and one16kbit OxRAM array. One FeRAM array and the OxRAM array can be operated simultaneously. Thecircuit leverages the OxRAM array to build a near-memory computing inference engine to accelerate theinference/feedforward pass of training, while FeRAM arrays store an 8-bit quantized version of thefloating-point weights optimized during training

    Spike-based beamforming using pMUT arrays for ultra-low power gesture recognition

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    International audienceSensor arrays constrain the power budget of battery-powered smart sensor as the analogue front-end (AFE), analogue-to-digital conversion (ADC) and digital signal processing is duplicated for each channel. By converting and processing the relevant information in the spiking domain, the energy consumption can be reduced by several orders of magnitude. We propose the first end-to-end ultra-low power Gesture Recognition (GR) system comprising an array of emitting and receiving piezoelectric micromachined ultrasonic transducers (pMUT), driving/sensing electronics, a novel spike-based beamforming strategy to extract the distance and angle information from incoming echoes without conventional ADCs and a Spiking Recurrent Neural Network (SRNN) for the GR. We experimentally demonstrate a classification accuracy of 86.0% on a dataset of five 3D gestures collected on our experimental setup

    Fully Integrated Spiking Neural Network with Analog Neurons and RRAM Synapses

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    International audienceThis paper presents, to the best of the authors' knowledge, the first complete integration of a Spiking Neural Network, combining analog neurons and Resistive RAM (RRAM)-based synapses. The implemented topology is a perceptron, aimed at performing MNIST classification. An existing framework was tailored for offline learning and weight quantization. The test chip, fabricated in 130nm CMOS, shows well-controlled integration of synaptic currents and no RRAM read disturb issue during inference tasks (at least 750M spikes). The classification accuracy is 84%, with a 3.6 pJ energy dissipation per spike at the synapse and neuron level (up to 5x lower vs. similar chips using formal coding)
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