Optimization of a Green Extraction of Polyphenols from Sweet Cherry (Prunus avium L.) Pulp

This work focused on the optimization of the ultrasound (US) extraction of polyphenols from sweet cherry pulp by monitoring cyanidin-3O-rutinoside, quercetin-3O-rutinoside, and trans-3-O-coumaroylquinic acid, representing the main anthocyanin, flavonol, and hydroxycinnamate, respectively, identified in the extracts through chromatographic analyses (HPLC-DAD), as output variables. The optimization was performed following a two-level central composite design and the influence of the selected independent variables (i.e., extraction time and solid to solvent ratio) was checked through the response surface methodology. The maximum recovery of the phenolic compounds was obtained at 3 min and 0.25 g/mL in water/ethanol (1:1, v/v) at a set temperature (25 °C), sonication power (100 W), and sonication frequency (37 kHz). Subsequent validation experiments proved the effectiveness and reliability of the gathered mathematical models in defining the best ultrasound-assisted extraction conditions

Olive sound: A sustainable radical innovation

Olive Sound is the acronym of a Horizon 2020 European Project aimed at the development of a high-flow oil extraction plant, the Sono-Heat-Exchanger, which combines ultrasound and heat exchange in order to break, through a radical innovation model in the oil mill, the historical paradigm that sees as inversely correlated the oil yield and the content of bio-phenols. These compounds are biologically active molecules that transform the product, extra virgin olive oil, from a mere condiment into a functional food. The primary objective of the project, financially supported by the European Union through the “Fast Track to Innovation” program, is the development of a product “ready for the market” (TRL 9) capable of making the involved companies more competitive while increasing the competitiveness of European extra virgin olive oil in the international context

Simulations and comparisons of basic analog and digital circuit blocks employing Tunnel FETs and conventional FinFETs

NTRODUCTION \u2015 In the past decade the Tunnel Field Effect Transistor (TFET) relying on band-to-band tunneling (BTBT) has emerged as one of the most promising small slope FETs able to achieve a subthreshold swing (SS) below the room temperature 60 mV/dec limit of conventional MOSFET [1]. Many simulation studies attributed to TFETs the potential to outperform conventional MOSFETs in the ultra-low voltage domain (VDD < 0.4 V) in both analog [2-3] and digital [4-7] applications. However, only basic digital and analog circuits have been fabricated up to date, such as current mirrors [8] and inverter gates [9]. As for semiconductor materials, III-V hetero-structure TFETs may be able to achieve a sub-thermal SS in a wide current range and, at the same time, very competitive on currents [1], as demonstrated by a recently fabricated vertical InAs/GaAsSb/GaSb nanowire n-type TFETs [10]. The aim of this work is to benchmark a complementary III-V TFET technology platform against the mainstream FinFET reference, by considering basic building blocks of digital and analog applications. To this purpose, we selected a complementary III-V TFET technology platform designed and optimized using full quantum simulations in [11], where n- and p-type TFET pairs are realized in the same InAs/AlGaSb material system. The use of such devices allowed us to remove the excessively optimistic assumption of perfectly symmetric n- and p-type TFETs, very frequently embraced in previous simulation studies (e.g. in [2, 7]). We present circuit-level simulations performed on current mirrors and inverter-based logic blocks, which are identified as basic topologies representative of the analog and digital design realms, respectively. Similar benchmarking results for the same technology platforms have been obtained by focusing the comparison on more complicated circuit blocks [3], [5] and [6]

Hemp: An Alternative Source for Various Industries and an Emerging Tool for Functional Food and Pharmaceutical Sectors

Hemp is a high-value crop that originated in Central Asia and is a historic but emerging cultivated plant. It may be grown for fiber, food, paper making, textiles, and therapeutic reasons. In the 21st century, market interest in hemp and its products has notably increased because seed portions can be utilized in the agri-food business, the woody component of the stem can be used in green buildings, the outer layer of the stems can be used in the textile industry, and the extraction of bioactive components from roots can play a vital role in the pharmacological industries. Hemp has recently been demonstrated to be a viable alternative for economies built on synthetic materials by the food, pharmaceutical, textiles, paper, building, and energy industries, among others. As a result, the goal of this study is to assemble the significant advancements in hemp, as well as to identify research gaps and research direction opportunities. The hemp plant will be provided more encouragement to be grown and be used. Many applications of hemp may be pushed to the next level for both producing a green environment and profit. A strong vision and a well-defined plan will pave the path for the discovery of new technologies and concepts

Digital and analog TFET circuits: Design and benchmark

In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10 nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDDlower than 0.4 V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions

Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing

Smart material implication (SIMPLY) logic has been recently proposed for the design of energy-efficient Logic-in-Memory (LIM) architectures based on non-volatile resistive memory devices. The SIMPLY logic is enabled by adding a comparator to the conventional IMPLY scheme. This allows performing a preliminary READ operation and hence the SET operation only in the case it is actually required. This work explores the SIMPLY logic scheme using nanoscale spin-transfer torque magnetic tunnel junction (STT-MTJ) devices. The performance of the STT-MTJ based SIMPLY architecture is analyzed by varying the load resistor and applied voltages to implement both READ and SET operations, while also investigating the effect of temperature on circuit operation. Obtained results show an existing tradeoff between error rate and energy consumption, which can be effectively managed by properly setting the values of load resistor and applied voltages. In addition, our analysis proves that tracking the temperature dependence of the MTJ properties through a proportional to absolute temperature (PTAT) reference voltage at the input of the comparator is beneficial to mitigate the reliability degradation under temperature variations

Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits

In this work, a complementary InAs/Al0.05Ga0.95Sb tunnel field-effect-Transistor (TFET) virtual technology platform is benchmarked against the projection to the CMOS FinFET 10-nm node, by means of device and basic circuit simulations. The comparison is performed in the ultralow voltage regime (below 500 mV), where the proposed III-V TFETs feature ON-current levels comparable to scaled FinFETs, for the same low-operating-power OFF-current. Due to the asymmetrical n-and p-Type I-V exts , trends of noise margins and performances are investigated for different Wp/Wn ratios. Implications of the device threshold voltage variability, which turned out to be dramatic for steep slope TFETs, are also addressed