Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications

The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing in-memory computing (IMC) solutions to the fore. Since large data sets are usually stored in nonvolatile memory (NVM), various solutions have been proposed based on emerging memories, such as OxRAM, that rely mainly on area hungry, one transistor (1T) one OxRAM (1R) bit-cell. To tackle this area issue, while keeping the programming control provided by 1T1R bit-cell, we propose to combine gate-all-around stacked junctionless nanowires (1JL) and OxRAM (1R) technology to create a 3-D memory pillar with ultrahigh density. Nanowire junctionless transistors have been fabricated, characterized, and simulated to define current conditions for the whole pillar. Finally, based on Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, we demonstrated successfully scouting logic operations up to three-pillar layers, with one operand per layer

On-Line Adjustable Precision Computing

International audienc

On-Line Adjustable Precision Computing

International audienc

Clocked and event-driven redundant adjustable precision computing

International audienceConnected mobile applications, known as the Internet of Things (IoT), require deploying extensive efforts to optimize power consumption and to improve the system performance at the same time. One way to reach this goal is based on sacrificing the computing precision by adopting different approximate computing methodologies for boosting system performance and reducing the power consumption. In this work, Adjustable Precision Computing (APC) based on redundant and on-line arithmetic operators is introduced. It provides the possibility to adapt the computing precision at will, depending on the performance and/or power requirements of the application. The proposed approach supplies an efficient power and area optimized solution with higher performance and without compromising the computing precision. Indeed, the APC innovative architecture allows users to dynamically modify the system computation precision, as required. The adjudication of asynchronous control, instead of the traditional synchronous clocking, enhances even more the impact of the APC. The results of both synchronous and asynchronous implementation examples are presented, showing the efficiency of the APC approach

Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges

International audienceThe energy consumption associated with data movement between memory and processing units is the main roadblock for the massive deployment of edge Artificial Intelligence. To overcome this challenge, Binarized Neural Networks (BNN) coupled with RRAM-based in-or nearmemory computing constitute an appealing solution. However, proposals from the literature tend to involve significant periphery circuit overheads. In this work, we propose and demonstrate experimentally, on a fabricated hybrid CMOS-RRAM integrated circuit, a robust in-memory XOR operation based on a 2T2R cell used in a resistive bridge manner. With this architecture, the RRAM read operation and the BNN multiplication operation can be achieved simultaneously, requiring only inverters connected to each Source Line of the memory array, and the BNN POPCOUNT operation can be realized with an analog capacitive neuron. Based on our measurements and extensive Monte Carlo simulations, we validate that this approach is suitable for large neurons with a low error rate (3.12% of error considering the full range of POPCOUNT values). Based on the circuit simulation results, we highlight the resilience of this approach at the network level, with a minimal accuracy degradation on the MNIST (0.07%) and CIFAR-10 (0.35%) tasks with regards to software solutions

3D RRAMs with Gate-All-Around Stacked Nanosheet Transistors for In-Memory-Computing

International audienceThis paper explores a novel 3D one transistor / one RRAM (1T1R) memory cube. The proposed architecture integrates HfO2-based OxRAM with select junctionless (JL) transistors based on low-voltage Gate-All-Around (GAA) stacked NanoSheet (NS) technology. A bitcell size of 23.9×F 2 /N is achieved ('N' being the number of stacked-NS) as well as a very high write and read parallelism. Extensive characterization of JL transistors and OxRAMs is performed to show their ability to be co-integrated inside a same 1T1R memory cell. Electrical characterization of 4kbits OxRAM arrays shows a large memory window (HRS/LRS=20) up to 10 4 cycles with a current compliance of 150µA, compatible with the performances of our JL transistors. Then, we experimentally demonstrate scouting logic operations capability with 2 operands, which should be extended to 4 operands thanks to an original two cells/bit "double coding" scheme assessed by SPICE simulations. Finally, we evidenced that this computing scheme is 2 times more energy efficient than a write-verify approach. I. INTRODUCTIO

An extendable optical fibre probe survey meter for naturally occurring radioactive material (NORM) and other weak emitters

Abstract We have developed a radioluminescence-based survey meter for use in industries in which there is involvement in naturally occurring radioactive material (NORM), also in support of those needing to detect other weak emitters of radiation. The functionality of the system confronts particular shortcomings of the handheld survey meters that are currently being made use of. The device couples a LYSO:Ce scintillator with a photodetector via a polymer optical fibre waveguide, allowing for "intrinsically safe" inspection within pipework, separators, valves and other such component pieces. The small-diameter optical fibre probe is electrically passive, immune to electromagnetic interference, and chemically inert. The readout circuit is entirely incorporated within a handheld casing housing a silicon photomultiplier (SiPM) detection circuit and a microprocessor circuit connected to an LCD display. A 15 m long flexible PMMA optical fibre waveguide is butt coupled to an ABS plastic probe that retains the LYSO:Ce scintillator. Initial tests have included the use of lab-based mixed gamma-ray sources, measurements being made in concert with a reference conventional GM survey-meter. Characterization, via NORM sources at a decontamination facility, has shown useful sensitivity, covering the dose-rate range 0.10- to 28 µSv h−1 (R-squared 0.966), extending to 80 µSv/h as demonstrated in use of a Cs-137 source. The system is shown to provide an effective tool for detection of radioactivity within hard to access locations, in particular for sources emitting at low radiation levels, down to values that approach background

Designing networks of resistively-coupled stochastic Magnetic Tunnel Junctions for energy-based optimum search

International audienceWe study recurrent networks of binary stochastic Magnetic Tunnel Junctions (sMTJ), aiming at efficiently solving computationally hard optimization problems. After validating a prototyping route, we investigate the impact of hybrid CMOS+MTJ building block variants on the quality of stochastic sampling, a key feature for optimum search in a complex landscape. In this regard, a better decoupling of the read/write paths gives spin-orbit torque (SOT) sMTJs an advantage over two-terminal spin-transfer torque (STT) sMTJs. We carry out a functional and power consumption analysis on asynchronous Ising networks in which coupling occurs through arrays of resistors, in the frame of Boolean satisfiability (SAT) solving. Using our SPICE model, we demonstrate that a 48-node SOT sMTJs network successfully converges to its ground state, factoring an 8-bit integer in 10µs with an estimated power consumption of 133µW/node