25 research outputs found

    Hydra: An Accelerator for Real-Time Edge-Aware Permeability Filtering in 65nm CMOS

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    Many modern video processing pipelines rely on edge-aware (EA) filtering methods. However, recent high-quality methods are challenging to run in real-time on embedded hardware due to their computational load. To this end, we propose an area-efficient and real-time capable hardware implementation of a high quality EA method. In particular, we focus on the recently proposed permeability filter (PF) that delivers promising quality and performance in the domains of HDR tone mapping, disparity and optical flow estimation. We present an efficient hardware accelerator that implements a tiled variant of the PF with low on-chip memory requirements and a significantly reduced external memory bandwidth (6.4x w.r.t. the non-tiled PF). The design has been taped out in 65 nm CMOS technology, is able to filter 720p grayscale video at 24.8 Hz and achieves a high compute density of 6.7 GFLOPS/mm2 (12x higher than embedded GPUs when scaled to the same technology node). The low area and bandwidth requirements make the accelerator highly suitable for integration into SoCs where silicon area budget is constrained and external memory is typically a heavily contended resource

    HR-SAR-Net: A Deep Neural Network for Urban Scene Segmentation from High-Resolution SAR Data

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    Synthetic aperture radar (SAR) data is becoming increasingly available to a wide range of users through commercial service providers with resolutions reaching 0.5m/px. Segmenting SAR data still requires skilled personnel, limiting the potential for large-scale use. We show that it is possible to automatically and reliably perform urban scene segmentation from next-gen resolution SAR data (0.15m/px) using deep neural networks (DNNs), achieving a pixel accuracy of 95.19% and a mean IoU of 74.67% with data collected over a region of merely 2.2km2{}^2. The presented DNN is not only effective, but is very small with only 63k parameters and computationally simple enough to achieve a throughput of around 500Mpx/s using a single GPU. We further identify that additional SAR receive antennas and data from multiple flights massively improve the segmentation accuracy. We describe a procedure for generating a high-quality segmentation ground truth from multiple inaccurate building and road annotations, which has been crucial to achieving these segmentation results

    Évolution du statut fonctionnel dùs 65 ans (Lc65+, n°1)

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    Quelle rĂ©ponse mĂ©dico-sociale faut-il apporter, face Ă  un vieillissement dĂ©mographique qui s’accĂ©lĂšre rapidement, depuis qu’en 2009 la vague des baby-boomers a abordĂ© le cap des 65 ans ? Combien de ressources faut-il prĂ©voir pour prendre en charge les dĂ©ficits fonctionnels frĂ©quents Ă  un grand Ăąge qu’aujourd’hui la plupart atteignent ? Pour rĂ©pondre Ă  ces questions il ne suffit pas de compter le nombre de personnes ĂągĂ©es, considĂ©rant qu’une fraction immuable nĂ©cessitera, demain comme hier, d’ĂȘtre aidĂ©e dans les activitĂ©s de la vie quotidienne. En effet, l’évolution de la santĂ© alors que la longĂ©vitĂ© augmente fait l’objet de thĂ©ories dont la plus populaire est celle d’une « compression de la morbiditĂ© ». Cette thĂ©orie veut qu’à un mĂȘme Ăąge les nouvelles gĂ©nĂ©rations, bĂ©nĂ©ficiant d’une plus grande longĂ©vitĂ©, soient en meilleure santĂ© que les gĂ©nĂ©rations prĂ©cĂ©dentes. La fraction des personnes devant ĂȘtre aidĂ©es Ă  un Ăąge donnĂ© ne serait donc pas fixe mais aurait diminuĂ© progressivement, et continuerait Ă  diminuer avec les gains de longĂ©vitĂ©. La thĂ©orie d’une compression de la morbiditĂ© est notamment portĂ©e par l’image que donnent les medias d’une gĂ©nĂ©ration de baby-boomers en parfaite santĂ©. Son impact peut ĂȘtre considĂ©rable si elle amĂšne avec optimisme Ă  ne pas dĂ©velopper les services mĂ©dico-sociaux de façon proportionnelle au vieillissement de la population. Elle reste cependant Ă  vĂ©rifier. Ce numĂ©ro des Essentiels se penche sur l’évolution du statut fonctionnel des personnes ĂągĂ©es. Les donnĂ©es de la cohorte Lc65+ (encadrĂ©) permettent d’étudier l’effet de l’ñge sur la frĂ©quence des difficultĂ©s fonctionnelles dans un Ă©chantillon reprĂ©sentatif de la population lausannoise suivi sur 13 ans. Elles permettent aussi de comparer « Ă  Ăąge Ă©gal » les personnes nĂ©es respectivement avant, pendant et Ă  la fin de la Seconde Guerre mondiale. Ces trois groupes, bien que sĂ©parĂ©s de 5 ans seulement, diffĂšrent significativement par les conditions socio-Ă©conomiques auxquelles ils ont Ă©tĂ© exposĂ©s

    Near-Memory Computing Architectures and Circuits for Ultra-Low Power Near-Sensor Processors

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    Artificial intelligence has started to permeate the entire technological fabric of our interconnected world and has long found its way to the network edge. Be it as part of novel biomedical devices that constantly monitor patient health, smart sensors in industrial settings where they drive the transformation from reactive- to pro-active maintenance in industry 4.0 or integrated into the next evolution of human-machine interfaces like XR, ML-enacting near-sensor circuits are omnipresent. The tight power and latency constraints of these applications fuel a paradigm shift in the hardware architecture domain, away from conventional von-Neumann-based computing, which is bound by the memory bandwidth bottleneck of the data- and control path. The "new golden age of computer architecture", as the famous computer pioneer David Patterson calls it, is marked by innovative Near- and In-memory architectures around conventional CMOS as well as novel "beyond-CMOS" technologies like PCM or ReRAM. However, many of these techniques are explored with an isolated, device-level-focused view, whereas advances at the system-level demand a holistic multi-objective optimization approach that involves hardware-software co-design and the exploration of new computing paradigms. This thesis investigates energy-efficient digital hardware architectures at both the circuit- and the system level and develops adequate strategies to enable energy-proportionality for general-purpose near-sensor analytics, i.e. the proportionality of energy consumption to vastly varying dynamic changes in workload compute intensity. We follow a multi-stage architectural approach where highly energy-efficient circuits based on the compute framework of Vector-Symbolic Architectures make up the first, always-on stage of our architecture "stack". In the second part of this thesis, we shift focus to the next, more computationally performant stage around heterogeneous compute cluster architectures, with an emphasis on the memory hierarchy. Here we propose a novel architectural design pattern to tightly couple NVM to the hardware accelerator. Both aspects are demonstrated and evaluated in several silicon realizations in 65nm bulk, 22nm FDSOI and 16nm FinFET technology

    Troubles psychiatriques, maintien à domicile et coopération : le point de vue des acteurs d'un réseau de soins

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    Dans le cadre de sa filiÚre psychiatrie communautaire, ARCOS a mis sur pied un groupe de travail " coopération en psychiatrie ". Le groupe est chargé de mettre en place un modÚle de coopération entre partenaires et de proposer des recommandations visant à améliorer la collaboration entre partenaires, afin de favoriser le maintien dans la communauté des personnes atteintes d'un handicap psychique. Cette recherche-action est issue des activités de ce groupe...[Auteurs, p. 8] [Table des matiÚres] 1. Introduction : constat des difficultés de coopération; l'articulation des soins spécialisés et de premier; etc. 2. Méthode. 3. Entretiens individuels : procédure d'analyse ; etc. 4. Entretiens collectifs (focus groups). 5. Discussion et perspectives: 5.1 Participer à l'élaboration d'une politique de santé mentale. 5.2 Introduire la dimension du réseau dans les institutions. 5.3 Les attentes des acteurs du réseau vis à vis des institutions

    Management of infections in critically ill returning travellers in the intensive care unit—II: clinical syndromes and special considerations in immunocompromised patients

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    This position paper is the second ESCMID Consensus Document on this subject and aims to provide intensivists, infectious disease specialists, and emergency physicians with a standardized approach to the management of serious travel-related infections in the intensive care unit (ICU) or the emergency department. This document is a cooperative effort between members of two European Society of Clinical Microbiology and Infectious Diseases (ESCMID) study groups and was coordinated by Hakan Leblebicioglu and Jordi Rello for ESGITM (ESCMID Study Group for Infections in Travellers and Migrants) and ESGCIP (ESCMID Study Group for Infections in Critically Ill Patients), respectively. A relevant expert on the subject of each section prepared the first draft which was then edited and approved by additional members from both ESCMID study groups. This article summarizes considerations regarding clinical syndromes requiring ICU admission in travellers, covering immunocompromised patients

    64-kB 65-nm GC-eDRAM With Half-Select Support and Parallel Refresh Technique

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    Gain-cell-embedded DRAM (GC-eDRAM) is an attractive alternative to traditional 6T SRAM, as it offers higher density, lower leakage power, and two-ported functionality. However, its refresh requirement also results in power consumption and memory access limitations. In this letter, we present a GC-eDRAM architecture designed to overcome the refresh disadvantages using a novel technique for improving the availability of the memory. In addition, by using a read-before-write mechanism, half select is supported. The macro avoids the need for supply boosting by employing 3T-1C bitcells and also integrates a replica bit line for optimal access timing to improve performance and power consumption. A 64- kB GC-eDRAM macro was fabricated in a 65- nm process technology, providing a 40% area reduction compared to a 6T SRAM cell, while achieving a 99.99% bit yield with a 16 mu s retention time.ISSN:2573-960
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