Proposal of a spin torque majority gate logic

A new spin based logic device is proposed. It is comprised of a common free ferromagnetic layer separated by a tunnel junction from three inputs and one output with separate fixed layers. It has the functionality of a majority gate and is switched by spin transfer torque. Validity of its logic operation is demonstrated by micromagnetic simulation. A version of such devices with perpendicular magnetization is examined. Switching encompasses moving domain walls. The device reuses most of the materials and structures from spin torque RAM, and is entirely compatible with CMOS technology.Comment: 14 pages, 4 figure

The number of negative modes of the oscillating bounces

The spectrum of small perturbations about oscillating bounce solutions recently discussed in the literature is investigated. Our study supports quite intuitive and expected result: the bounce with N nodes has exactly N homogeneous negative modes. Existence of more than one negative modes makes obscure the relation of these oscillating bounce solutions to the false vacuum decay processes.Comment: LaTex, 6 pages, including 3 figure

OPTIMAL AREA AND PERFORMANCE MAPPING OF K-LUT BASED FPGAS

FPGA circuits are increasingly used in many fields: for rapid prototyping of new products (including fast ASIC implementation), for logic emulation, for producing a small number of a device, or if a device should be reconfigurable in use (reconfigurable computing). Determining if an arbitrary, given wide, function can be implemented by a programmable logic block, unfortunately, it is generally, a very difficult problem. This problem is called the Boolean matching problem. This paper introduces a new implemented algorithm able to map, both for area and performance, combinational networks using k-LUT based FPGAs.k-LUT based FPGAs, combinational circuits, performance-driven mapping.