179 research outputs found

    形状記憶合金ワイヤを用いたロータリアクチュエータに関する研究

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    学位の種別:課程博士University of Tokyo(東京大学

    Investigation Of The Radiation Mechanism Of Heatsinks Based On Characteristic Mode Theory

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    Heatsinks may cause radiated emission and radio frequency interference problems when they are mounted on printed circuit boards. In this article, the radiation mechanism of heatsinks is systematically investigated using characteristic mode theory. The dipole moment is a commonly used equivalent source model for integrated circuits that drive radiated emission from heatsinks. On the basis of a simplified modal weighting coefficient formulation, the interactions between the dipole moment and the significant modes of the heatsink are efficiently evaluated, thus providing a clear physical insight into noise source placement. Finally, the grounding post design, a commonly used EMI mitigation method, is also discussed. The relative error of the mode-based field prediction is less than 3 dB compared with the full-wave simulation

    Design of an Impulse Radiating Antenna Using a Curved TEM-Wire Fed Parabola

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    A design procedure for a TEM-wire fed parabolic antenna is given for impulse radiation, which is suitable for low cost fabrication. A simple wire-type TEM horn and a parabolic reflector are used to achieve ultra-wide bandwidth and high directivity at the same time. Equations for parametric curves of a TEM-wire horn are presented and are used to investigate the relation among their shapes, bandwidth, and directivity. It is also found that wire separation near the focal point limits the high frequency directivity

    Analysis of Voltage Regulator Module (VRM) Noise Coupling to High-Speed Signals with VRM Via Designs

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    The Physical Noise Coupling Mechanism between Voltage Regulator Module (VRM) Noise Coupling to High-Speed Signal Traces is Analyzed and Different Noise Reduction Methods Are Analyzed for the First Time. the Rapid Switching of Field Effect Transistors (FETs) Creates an Unintentional Coupling Region Around the VRM. as High-Speed Traces Are Often Routed in the Inner Signal Layers of Printed Circuit Boards (PCBs) as Striplines for Signal Integrity, the VRM Switching Noise is Mainly Coupled from Noisy Power Vias to the Victim Traces Routed Around the VRM Region. to Analyze Different Coupling Reduction Methods in Practical High-Speed Channels, a Simplified PCB Design based on a High-Speed Server Platform is Proposed. Case Studies under Various Conditions Verifies the Most Effective VRM Noise Coupling Reduction Method. Different Design Parameters that Influence the VRM Noise Coupling Are Analyzed to Provide a Design Guide for High-Speed Channel Designers

    Methodology for Analyzing Coupling Mechanisms in RFI Problems based on PEEC

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    In This Article, a Method for Analyzing Coupling Mechanisms in Radio Frequency Interference (RFI) Problems is Proposed. the Partial Element Equivalent Circuit (PEEC) Method is First Used to Derive the Retarded Inductances and Capacitances between Different Mesh Cells. with the Introduction of a Novel Partitioning Algorithm, the Capacitive Coupling and Inductive Coupling between Arbitrary Layout Parts Can Be Quantified based on the Magnitude of the Displacement Current and Induced Voltage Drop. the Accuracy of the PEEC Models is Validated by Comparison with Different Commercial Tools. the Proposed Coupling Mechanism Analysis Flow Provides a Useful Prelayout Tool for RFI Risk Analysis

    First Demonstration of Ultra-Thin SiGe-Channel Junctionless Accumulation-Mode (JAM) Bulk FinFETs on Si Substrate with PN Junction-Isolation Scheme

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    A SiGe-channel junctionless-accumulation-mode (JAM) PMOS bulk FinFETs were successfully demonstrated on Si substrate with PN junction-isolation scheme for the first time. The JAM bulk FinFETs with fin width of 18 nm exhibits excellent subthreshold characteristics such as subthreshold swing of 64 mV/decade, drain-induced barrier lowering (DIBL) of 40 mV/V and high Ion/Ioff current ratio ( \u3e 1 x 105). The change of substrate bias from 0 to 5 V leads to the threshold voltage shift of 53 mV by modulating the effective channel thickness. When compared to the Si-channel bulk FinFETs with fin width of 18 nm, Si and SiGe channel devices exhibits comparable subthreshold swing and DIBL. For devices with longer fin width, SiGe channel devices exhibits much lower DIBL, indicating superior top-gate controllability and robustness to substrate bias compared to the Si channel devices. A zero temperature coefficient point was observed in the transfer curves as temperature increases from -120 to 120°C, confirming that mobility degradation is dominantly affected by phonon scattering mechanism
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