Development of inversion-mode and junctionless Indium-Gallium-Arsenide MOSFETs

This PhD covers the development of planar inversion-mode and junctionless Al2O3/In0.53Ga0.47As metal-oxidesemiconductor field-effect transistors (MOSFETs). An implant activation anneal was developed for the formation of the source and drain (S/D) of the inversionmode MOSFET. Fabricated inversion-mode devices were used as test vehicles to investigate the impact of forming gas annealing (FGA) on device performance. Following FGA, the devices exhibited a subthreshold swing (SS) of 150mV/dec., an ION/IOFF of 104 and the transconductance, drive current and peak effective mobility increased by 29%, 25% and 15%, respectively. An alternative technique, based on the fitting of the measured full-gate capacitance vs gate voltage using a selfconsistent Poisson-Schrödinger solver, was developed to extract the trap energy profile across the full In0.53Ga0.47As bandgap and beyond. A multi-frequency inversion-charge pumping approach was proposed to (1) study the traps located at energy levels aligned with the In0.53Ga0.47As conduction band and (2) separate the trapped charge and mobile charge contributions. The analysis revealed an effective mobility (μeff) peaking at ~2850cm2/V.s for an inversion-charge density (Ninv) = 7*1011cm2 and rapidly decreasing to ~600cm2/V.s for Ninv = 1*1013 cm2, consistent with a μeff limited by surface roughness scattering. Atomic force microscopy measurements confirmed a large surface roughness of 1.95±0.28nm on the In0.53Ga0.47As channel caused by the S/D activation anneal. In order to circumvent the issue relative to S/D formation, a junctionless In0.53Ga0.47As device was developed. A digital etch was used to thin the In0.53Ga0.47As channel and investigate the impact of channel thickness (tInGaAs) on device performance. Scaling of the SS with tInGaAs was observed for tInGaAs going from 24 to 16nm, yielding a SS of 115mV/dec. for tInGaAs = 16nm. Flat-band μeff values of 2130 and 1975cm2/V.s were extracted on devices with tInGaAs of 24 and 20nm, respectivel

Multi-frequency inversion-charge pumping for charge separation and mobility analysis in high-k/InGaAs metal-oxide-semiconductor field-effect transistors

An alternative multi-frequency inversion-charge pumping (MFICP) technique was developed to directly separate the inversion charge density (N-inv) from the trapped charge density in high-k/InGaAs metal-oxide-semiconductor field-effect transistors (MOSFETs). This approach relies on the fitting of the frequency response of border traps, obtained from inversion-charge pumping measurements performed over a wide range of frequencies at room temperature on a single MOSFET, using a modified charge trapping model. The obtained model yielded the capture time constant and density of border traps located at energy levels aligned with the InGaAs conduction band. Moreover, the combination of MFICP and pulsed I-d-V-g measurements enabled an accurate effective mobility vs N-inv extraction and analysis. The data obtained using the MFICP approach are consistent with the most recent reports on high-k/InGaAs. (C) 2015 AIP Publishing LLC

Characterisation of a novel electron beam lithography resist, SML and its comparison to PMMA and ZEP resists

As transistor dimensions continue to diminish, techniques for fabrication need to be adapted. In particular, crystal recovery post ion implantation is required due to destructive ion bombardment inducing crystal damage including amorphization. Here, we report a study on the post-implant recrystallization in germanium (Ge) nanowires (NWs) following gallium (Ga) ion doping. In this work a variation of NW diameters and orientations were irradiated and annealed in situ to investigate the mechanism of recrystallization. An added complication of misorientation of crystal grains increases the complexity of crystal recovery for suspended NWs. We show that when the misorientation is prevented, by leaving a crystal link between two seeds and providing a rigid support, recrystallization occurs primarily via solid phase epitaxial growth (SPEG). Finally, we demonstrate that top-down fabricated Ge NWs on insulator can be recovered with no extended defects. This work highlights both experimentally and through molecular dynamic simulations the importance of engineering crystal recovery in Ge NWs which may have potential for next-generation complementary metal-oxide semiconductor (CMOS) devices

A systematic study of (NH4)(2)S passivation (22%, 10%, 5%, or 1%) on the interface properties of the Al2O3/In0.53Ga0.47As/InP system for n-type and p-type In0.53Ga0.47As epitaxial layers

In this work, we present the results of an investigation into the effectiveness of varying ammonium sulphide (NH4)(2)S concentrations in the passivation of n-type and p-type In0.53Ga0.47As. Samples were degreased and immersed in aqueous (NH4)(2)S solutions of concentrations 22%, 10%, 5%, or 1% for 20 min at 295 K, immediately prior to atomic layer deposition of Al2O3. Multi-frequency capacitance-voltage (C-V) results on capacitor structures indicate that the lowest frequency dispersion over the bias range examined occurs for n-type and p-type devices treated with the 10% (NH4)(2)S solution. The deleterious effect on device behavior of increased ambient exposure time after removal from 10% (NH4)(2)S solution is also presented. Estimations of the interface state defect density (D-it) for the optimum 10% (NH4)(2)S passivated In0.53Ga0.47As devices extracted using an approximation to the conductance method, and also extracted using the temperature-modified high-low frequency C-V method, indicate that the same defect is present over n-type and p-type devices having an integrated D-it of similar to 2.5 x 10(12) cm(-2) (+/- 1 x 10(12) cm(-2)) with the peak density positioned in the middle of the In0.53Ga0.47As band gap at approximately 0.37 eV (+/- 0.03 eV) from the valence band edge. Both methods used for extracting D-it show very good agreement, providing evidence to support that the conductance method can be applied to devices incorporating high-k oxides on In0.53Ga0.47As. (C) 2011 American Institute of Physics. [doi: 10.1063/1.3533959

Resist-substrate interface tailoring for generating high density arrays of Ge and Bi2Se3 nanowires by electron beam lithography

The authors report a chemical process to remove the native oxide on Ge and Bi2Se3 crystals, thus facilitating high-resolution electron beam lithography (EBL) on their surfaces using a hydrogen silsesquioxane (HSQ) resist. HSQ offers the highest resolution of all the commercially available EBL resists. However, aqueous HSQ developers such as NaOH and tetramethylammonium hydroxide have thus far prevented the fabrication of high-resolution structures via the direct application of HSQ to Ge and Bi2Se3, due to the solubility of components of their respective native oxides in these strong aqueous bases. Here we provide a route to the generation of ordered, high-resolution, high-density Ge and Bi2Se3 nanostructures with potential applications in microelectronics, thermoelectric, and photonics devices.                        

Effect of low temperature RF plasma treatment on electrical properties of junctionless InGaAs MOSFETs

In this paper, we study the effect of low-temperature RF plasma treatment in forming gas (10%H2+90%N2) on the electrical characteristics of junctionless MOSFETs with n-In0.53Ga0.47As channel and an Al2O3 gate dielectric. The impact of plasma power density on the device parameters is investigated. It is found that RF plasma annealing with a low power density (0.5 W/cm2) at 150°C for 10 min provides substantial improvement of source/drain contacts resistance and the carrier mobility resulting in a considerable increase of the on-state current and transconductance. It also improves the subthreshold slope and reduces the fixed positive charge in Al2O3 under the gate, shifting the threshold voltage toward positive values. It is demonstrated that non-thermal factors play a principle role in modification of electrical properties of the JL MOSFETs under RF plasma treatment. Such treatment may be an efficient tool for the improvement of the performance of the advanced MOSFETs with III-V channel materials

Characterisation of a novel electron beam lithography resist, SML and its comparison to PMMA and ZEP resists

As transistor dimensions continue to diminish, techniques for fabrication need to be adapted. In particular, crystal recovery post ion implantation is required due to destructive ion bombardment inducing crystal damage including amorphization. Here, we report a study on the post-implant recrystallization in germanium (Ge) nanowires (NWs) following gallium (Ga) ion doping. In this work a variation of NW diameters and orientations were irradiated and annealed in situ to investigate the mechanism of recrystallization. An added complication of misorientation of crystal grains increases the complexity of crystal recovery for suspended NWs. We show that when the misorientation is prevented, by leaving a crystal link between two seeds and providing a rigid support, recrystallization occurs primarily via solid phase epitaxial growth (SPEG). Finally, we demonstrate that top-down fabricated Ge NWs on insulator can be recovered with no extended defects. This work highlights both experimentally and through molecular dynamic simulations the importance of engineering crystal recovery in Ge NWs which may have potential for next-generation complementary metal-oxide semiconductor (CMOS) devices

Can Metal/Al2O3/In0.53Ga0.47As/InP MOSCAP properties translate to Metal/Al2O3/In0.53Ga0.47As/InP MOSFET characteristics?

In this paper we present the electrical characteristics of Metal/Al2O3/In0.53Ga0.47As/InP MOS capacitor (MOSCAP) structures formed using a relatively straightforward capacitor process flow and for MOSCAPs which experience the full process flow of an In0.53Ga0.47As n channel MOSFET. From analysis of the capacitance-voltage response over a range of ac signal frequencies fixed oxide charge densities and interface state concentrations are determined for the MOSCAP structures and the impact of forming gas annealing on oxide and interface state densities is presented. The MOSCAP results are compared to the properties of fully processed metal/Al2O3/In0.53Ga0.47As/InP n channel MOSFETs, and the results indicate that the findings from the MOSCAPS do translate to the measured InGaAs MOSFET characteristics

TiN/ZrO2/Ti/Al metal–insulator–metal capacitors with subnanometer CET using ALD-deposited ZrO2 for DRAM applications

We provide the first report of the structural and electrical properties of TiN/ZrO 2 /Ti/Al metal-insulator-metal capacitor structures, where the ZrO 2 thin film (7-8 nm) is deposited by ALD using the new zirconium precursor ZrD-04, also known as Bis(methylcyclopentadienyl) methoxymethyl. Measured capacitance-voltage ( C - V ) and current-voltage ( I - V ) characteristics are reported for premetallization rapid thermal annealing (RTP) in N 2 for 60 s at 400degC, 500degC, or 600degC. For the RTP at 400degC, we find very low leakage current densities on the order of nanoamperes per square centimeter at a gate voltage of 1 V and low capacitance equivalent thickness values of ~ 0.9 nm at a gate voltage of 0 V. The dielectric constant of ZrO 2 is 31 plusmn 2 after RTP treatment at 400degC