The Impact of Tunneling on the Subthreshold Swing in Sub-20 nm Asymmetric Double Gate MOSFETs

This paper analyzes the subthreshold swing in asymmetric double gate MOSFETs with sub-20 nm channel lengths. The analysis of the carrier transport in the subthreshold region of these nano scaled MOSFET includes tunneling as an important additional mechanism to the thermionic emission. It is found that the subthreshold swing is increasing due to tunneling current and that the performance of nano scaled MOSFETs is degraded. The degradation of the subthreshold swing due to tunneling is quantified using analytical potential distribution and Wentzel–Kramers–Brillouin (WKB) approximation in this paper. This analytical approach is verified by two dimensional simulation. It is shown that the degradation of subthreshold swing increases with both reduction of channel length and increase of channel thickness. We also show that the subthreshold swing is increasing in case of different top and bottom gate oxide thicknesses

Thermoresistance of p-Type 4H–SiC Integrated MEMS Devices for High-Temperature Sensing

There is an increasing demand for the development and integration of multifunctional sensing modules into power electronic devices that can operate in high temperature environments. Here, the authors demonstrate the tunable thermoresistance of p‐type 4H–SiC for a wide temperature range from the room temperature to above 800 K with integrated flow sensing functionality into a single power electronic chip. The electrical resistance of p‐type 4H–SiC is found to exponentially decrease with increasing temperature to a threshold temperature of 536 K. The temperature coefficient of resistance (TCR) shows a large and negative value from −2100 to −7600 ppm K−1, corresponding to a thermal index of 625 K. From the threshold temperature of 536–846 K, the electrical resistance shows excellent linearity with a positive TCR value of 900 ppm K−1. The authors successfully demonstrate the integration of p–4H–SiC flow sensing functionality with a high sensitivity of 1.035 μA(m s−1)−0.5 mW−1. These insights in the electrical transport of p–4H–SiC aid to improve the performance of p–4H–SiC integrated temperature and flow sensing systems, as well as the design consideration and integration of thermal sensors into 4H–SiC power electronic systems operating at high temperatures of up to 846 K

Piezo-Hall effect in single crystal p-type 3C-SiC(100) thin film grown by low pressure chemical vapor deposition

This article reports the first results on piezo-Hall effect in single crystal p-type 3C–SiC(100) Hall devices. Single crystal p-type 3C–SiC(100) was grown by low pressure chemical vapor deposition, and Hall devices were fabricated using the conventional photolithography and dry etching processes. An experimental setup capable of applying stress during Hall-effect measurements was designed to measure the piezo-Hall effect. The piezo-Hall effect is quantified by directly observing the variation in magnetic field sensitivity of the Hall devices upon an applied stress. The piezo-Hall coefficient P12 characterized by these measurements is found to be 6.4 × 10−11 Pa−1

Piezoresistive effect in p-Type 3C-SiC at high temperatures characterized using Joule heating

Cubic silicon carbide is a promising material for Micro Electro Mechanical Systems (MEMS) applications in harsh environ-ments and bioapplications thanks to its large band gap, chemical inertness, excellent corrosion tolerance and capability of growth on a Si substrate. This paper reports the piezoresistive effect of p-type single crystalline 3C-SiC characterized at high temperatures, using an in situ measurement method. The experimental results show that the highly doped p-type 3C-SiC possesses a relatively stable gauge factor of approximately 25 to 28 at temperatures varying from 300 K to 573 K. The in situ method proposed in this study also demonstrated that, the combination of the piezoresistive and thermoresistive effects can increase the gauge factor of p-type 3C-SiC to approximately 20% at 573 K. The increase in gauge factor based on the combination of these phenomena could enhance the sensitivity of SiC based MEMS mechanical sensors

Aluminum induced in situ crystallization of amorphous SiC

Experimental evidence of aluminum induced in situ crystallization of amorphous SiC is presented. The deposition of SiC films on Si substrates was performed using low pressure chemical vapor deposition method at 600 degrees C with concurrent supply of Al(CH(3))(3) and H(3)SiCH(3). Transmission electron micrographs confirm the presence of nanocrystals, whereas capacitance-voltage measurements demonstrate that the deposited films are p type doped. A crystallization mechanism is proposed based on the classic theory of nucleation in the growth rate limited regime. The introduction of Al(CH(3))(3) enhances the surface reaction and increases the supersaturation, which reduces the activation energy for nucleation

Electrically Active Defects in SiC Power MOSFETs

The performance and reliability of the state-of-the-art power 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) are affected by electrically active defects at and near the interface between SiC and the gate dielectric. Specifically, these defects impact the channel-carrier mobility and threshold voltage of SiC MOSFETs, depending on their physical location and energy levels. To characterize these defects, techniques have evolved from those used for Si devices to techniques exclusively designed for the SiC MOS structure and SiC MOSFETs. This paper reviews the electrically active defects at and near the interface between SiC and the gate dielectric in SiC power MOSFETs and MOS capacitors. First, the defects are classified according to their physical locations and energy positions into (1) interface traps, (2) near interface traps with energy levels aligned to the energy gap, and (3) near-interface traps with energy levels aligned to the conduction band of SiC. Then, representative published results are shown and discussed for each class of defect

Electrically Active Defects in SiC Power MOSFETs

The performance and reliability of the state-of-the-art power 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) are affected by electrically active defects at and near the interface between SiC and the gate dielectric. Specifically, these defects impact the channel-carrier mobility and threshold voltage of SiC MOSFETs, depending on their physical location and energy levels. To characterize these defects, techniques have evolved from those used for Si devices to techniques exclusively designed for the SiC MOS structure and SiC MOSFETs. This paper reviews the electrically active defects at and near the interface between SiC and the gate dielectric in SiC power MOSFETs and MOS capacitors. First, the defects are classified according to their physical locations and energy positions into (1) interface traps, (2) near interface traps with energy levels aligned to the energy gap, and (3) near-interface traps with energy levels aligned to the conduction band of SiC. Then, representative published results are shown and discussed for each class of defect