Magnetic Random Access Memory based non-volatile asynchronous Muller cell for ultra-low power autonomous applications

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Non-volatility for ultra-low power asynchronous circuits in hybrid CMOS/magnetic technology

International audienceThis paper addresses the power reduction techniques for the ultra-low power integrated circuits. We propose to implement non-volatile asynchronous circuits which will have a quasi-zero leakage consumption, almost instant back-up and wake-up time and will be robust to unstable supply environments. This paper presents the implementation of the non-volatile C-element and Half-Buffer, based on hybrid technology incorporating 28nm CMOS FD-SOI and 40nm STT-MRAM magnetic technologies. We discuss our recent simulation results of the proposed non-volatile blocks and as well more complex structures based on them. We derive the criteria of the implementation efficiency and compare the conventional asynchronous blocks with the proposed non-volatile ones

Ultra-low power volatile and non-volatile asynchronous circuits using back-biasing

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Infrastructures for Education, Research and Industry: CMOS and MEMS for BioMed

International audienceInfrastructures to provide access to custom integrated hardware manufacturing facilities are important because they allow Students and Researchers to access professional facilities at a reasonable cost, and they allow Companies to access small volume production, otherwise difficult to obtain directly from manufacturers. This paper is reviewing the most recent developments at CMP, focusing on the manufacturing of various kinds of MEMS. These MEMS are hardware vehicles for many BioMed applications. Various examples are provided in the paper. Such infrastructures may help the BioMed community the same way they helped the Microelectronics community at the time of the VLSI revolution

Comparison of Verilog-A compact modelling strategies for spintronic devices

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Spin Orbit Torque memory for non-volatile microprocessor caches

Magnetic spin-based memory technologies are a promising solution to overcome the incoming limits of microelectronics. Nevertheless, the long write latency and high write energy of these memory technologies compared to SRAM make it difficult to use these for fast microprocessor memories, such as L1- Caches. However, the recent advent of the Spin Orbit Torque (SOT) technology changed the story: indeed, it potentially offers a writing speed comparable to SRAM with a much better density as SRAM and an infinite endurance, paving the way to a new paradigm in processor architectures, with introduction of non- volatility in all the levels of the memory hierarchy towards full normally-off and instant-on processors. This paper presents a full design flow, from device to system, allowing to evaluate the potential of SOT for microprocessor cache memories and very encouraging simulation results using this framework

Infrastructures for Education and Research: from National Initiatives to global operations

Infrastructures to provide access to custom integrated hardware manufacturing facilities are important because they allow Students and Researchers to access professional facilities at a reasonable cost, and they allow Companies to access small volume production, otherwise difficult to obtain directly from manufacturers. In the late 70s/early 80s, pioneering integrated circuits Multi-Chip Projects / Multi-Project Wafers initiatives have been launched in Europe, Asia, and North America. Some of these initiatives work together and today a worldwide cooperation has been established by the most experienced. The paper review these initiatives and the motivations for a global cooperation scheme

Correlation between 1064 nm laser attack and thermal behavior in STT-MRAM

International audienceIn this paper, the impact of a 1064 nm laser attack on an STT-MRAM cell is experimentally studied in real-time, for the first time, during reading and writing operations, in order to understand the behavior of a sensing circuit under a temperature variation from 25 °C to 105 °C. This must be considered for the implementation of a hybrid CMOS/MRAM Light-Weight Cryptography circuit, to overcome a laser attack. We highlight a reading current variation during the laser shots, that can impact the sensing circuits. The switching probability between the two states has been measured as well as the impact of the irradiation time, laser power, and cell size. We correlate the results with electrical characterizations in a wide range of temperatures, demonstrating the 1064 nm laser attack thermally affects the STT-MRAM behavior. In conclusion, suitable countermeasures can be adopted

Experimental analysis on stochastic behavior of preswitching time in STT-MRAM

International audienceIn this paper we present an experimental study on the preswitching time of Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) with a resistance area R.A. ~ 12 Ω.μm2, for both transitions, Anti-Parallel to Parallel state and vice versa. A set of measurements is carried out operating at different applied voltages and temperatures ranging from 25 °C to 90 °C. As main results of our analysis, we show the decrease of the preswitching time with temperature increase. The Arrhenius law enables the extraction of the activation energy required to switch the cell in both states. Finally, we establish the relevant state transition probabilities using the Weibull distribution that best fits our results. The Weibull parameters highlight the preswitching time stochasticity and the variability of the switching characteristics of the STT-MRAM device, useful in high reliability applications